HMAC Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 15.660s 1.815ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.990s 42.411us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.980s 31.937us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 16.230s 1.645ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 9.140s 1.191ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 15.157m 92.701ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.980s 31.937us 20 20 100.00
hmac_csr_aliasing 9.140s 1.191ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.800m 14.506ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.815m 3.623ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.394m 189.171ms 5 5 100.00
hmac_test_sha384_vectors 45.338m 433.753ms 5 5 100.00
hmac_test_sha512_vectors 45.584m 277.683ms 5 5 100.00
hmac_test_hmac256_vectors 1.164m 3.450ms 5 5 100.00
hmac_test_hmac384_vectors 1.522m 2.231ms 5 5 100.00
hmac_test_hmac512_vectors 2.281m 17.055ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.169m 14.937ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 30.318m 8.391ms 50 50 100.00
V2 error hmac_error 4.513m 26.603ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.664m 13.362ms 50 50 100.00
V2 save_and_restore hmac_smoke 15.660s 1.815ms 50 50 100.00
hmac_long_msg 3.800m 14.506ms 50 50 100.00
hmac_back_pressure 1.815m 3.623ms 50 50 100.00
hmac_datapath_stress 30.318m 8.391ms 50 50 100.00
hmac_burst_wr 1.169m 14.937ms 50 50 100.00
hmac_stress_all 2.107h 824.962ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 15.660s 1.815ms 50 50 100.00
hmac_long_msg 3.800m 14.506ms 50 50 100.00
hmac_back_pressure 1.815m 3.623ms 50 50 100.00
hmac_datapath_stress 30.318m 8.391ms 50 50 100.00
hmac_wipe_secret 2.664m 13.362ms 50 50 100.00
hmac_test_sha256_vectors 11.394m 189.171ms 5 5 100.00
hmac_test_sha384_vectors 45.338m 433.753ms 5 5 100.00
hmac_test_sha512_vectors 45.584m 277.683ms 5 5 100.00
hmac_test_hmac256_vectors 1.164m 3.450ms 5 5 100.00
hmac_test_hmac384_vectors 1.522m 2.231ms 5 5 100.00
hmac_test_hmac512_vectors 2.281m 17.055ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 15.660s 1.815ms 50 50 100.00
hmac_long_msg 3.800m 14.506ms 50 50 100.00
hmac_back_pressure 1.815m 3.623ms 50 50 100.00
hmac_datapath_stress 30.318m 8.391ms 50 50 100.00
hmac_burst_wr 1.169m 14.937ms 50 50 100.00
hmac_error 4.513m 26.603ms 50 50 100.00
hmac_wipe_secret 2.664m 13.362ms 50 50 100.00
hmac_test_sha256_vectors 11.394m 189.171ms 5 5 100.00
hmac_test_sha384_vectors 45.338m 433.753ms 5 5 100.00
hmac_test_sha512_vectors 45.584m 277.683ms 5 5 100.00
hmac_test_hmac256_vectors 1.164m 3.450ms 5 5 100.00
hmac_test_hmac384_vectors 1.522m 2.231ms 5 5 100.00
hmac_test_hmac512_vectors 2.281m 17.055ms 5 5 100.00
hmac_stress_all 2.107h 824.962ms 50 50 100.00
V2 stress_all hmac_stress_all 2.107h 824.962ms 50 50 100.00
V2 alert_test hmac_alert_test 0.640s 17.149us 50 50 100.00
V2 intr_test hmac_intr_test 0.650s 18.025us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.160s 279.374us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.160s 279.374us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.990s 42.411us 5 5 100.00
hmac_csr_rw 0.980s 31.937us 20 20 100.00
hmac_csr_aliasing 9.140s 1.191ms 5 5 100.00
hmac_same_csr_outstanding 2.480s 114.665us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.990s 42.411us 5 5 100.00
hmac_csr_rw 0.980s 31.937us 20 20 100.00
hmac_csr_aliasing 9.140s 1.191ms 5 5 100.00
hmac_same_csr_outstanding 2.480s 114.665us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.000s 153.163us 5 5 100.00
hmac_tl_intg_err 4.650s 1.748ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.650s 1.748ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 15.660s 1.815ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.392h 64.019ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.61 95.40 97.17 100.00 94.12 98.27 98.48 99.85

Past Results