HMAC Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 15.470s 2.534ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.000s 20.414us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.960s 72.942us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 16.190s 1.649ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 9.240s 597.594us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 16.988m 424.260ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.960s 72.942us 20 20 100.00
hmac_csr_aliasing 9.240s 597.594us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.244m 29.512ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.561m 10.282ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.480m 112.718ms 5 5 100.00
hmac_test_sha384_vectors 42.729m 834.783ms 5 5 100.00
hmac_test_sha512_vectors 42.576m 298.390ms 5 5 100.00
hmac_test_hmac256_vectors 1.286m 31.382ms 5 5 100.00
hmac_test_hmac384_vectors 1.723m 27.175ms 5 5 100.00
hmac_test_hmac512_vectors 2.297m 29.849ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.140m 3.268ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 31.881m 33.866ms 50 50 100.00
V2 error hmac_error 3.928m 4.172ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.553m 11.275ms 50 50 100.00
V2 save_and_restore hmac_smoke 15.470s 2.534ms 50 50 100.00
hmac_long_msg 3.244m 29.512ms 50 50 100.00
hmac_back_pressure 1.561m 10.282ms 50 50 100.00
hmac_datapath_stress 31.881m 33.866ms 50 50 100.00
hmac_burst_wr 1.140m 3.268ms 50 50 100.00
hmac_stress_all 1.484h 220.188ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 15.470s 2.534ms 50 50 100.00
hmac_long_msg 3.244m 29.512ms 50 50 100.00
hmac_back_pressure 1.561m 10.282ms 50 50 100.00
hmac_datapath_stress 31.881m 33.866ms 50 50 100.00
hmac_wipe_secret 2.553m 11.275ms 50 50 100.00
hmac_test_sha256_vectors 11.480m 112.718ms 5 5 100.00
hmac_test_sha384_vectors 42.729m 834.783ms 5 5 100.00
hmac_test_sha512_vectors 42.576m 298.390ms 5 5 100.00
hmac_test_hmac256_vectors 1.286m 31.382ms 5 5 100.00
hmac_test_hmac384_vectors 1.723m 27.175ms 5 5 100.00
hmac_test_hmac512_vectors 2.297m 29.849ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 15.470s 2.534ms 50 50 100.00
hmac_long_msg 3.244m 29.512ms 50 50 100.00
hmac_back_pressure 1.561m 10.282ms 50 50 100.00
hmac_datapath_stress 31.881m 33.866ms 50 50 100.00
hmac_burst_wr 1.140m 3.268ms 50 50 100.00
hmac_error 3.928m 4.172ms 50 50 100.00
hmac_wipe_secret 2.553m 11.275ms 50 50 100.00
hmac_test_sha256_vectors 11.480m 112.718ms 5 5 100.00
hmac_test_sha384_vectors 42.729m 834.783ms 5 5 100.00
hmac_test_sha512_vectors 42.576m 298.390ms 5 5 100.00
hmac_test_hmac256_vectors 1.286m 31.382ms 5 5 100.00
hmac_test_hmac384_vectors 1.723m 27.175ms 5 5 100.00
hmac_test_hmac512_vectors 2.297m 29.849ms 5 5 100.00
hmac_stress_all 1.484h 220.188ms 50 50 100.00
V2 stress_all hmac_stress_all 1.484h 220.188ms 50 50 100.00
V2 alert_test hmac_alert_test 0.680s 44.983us 50 50 100.00
V2 intr_test hmac_intr_test 0.660s 28.689us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.600s 435.472us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.600s 435.472us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.000s 20.414us 5 5 100.00
hmac_csr_rw 0.960s 72.942us 20 20 100.00
hmac_csr_aliasing 9.240s 597.594us 5 5 100.00
hmac_same_csr_outstanding 2.440s 153.427us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.000s 20.414us 5 5 100.00
hmac_csr_rw 0.960s 72.942us 20 20 100.00
hmac_csr_aliasing 9.240s 597.594us 5 5 100.00
hmac_same_csr_outstanding 2.440s 153.427us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.100s 81.956us 5 5 100.00
hmac_tl_intg_err 4.480s 1.560ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.480s 1.560ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 15.470s 2.534ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.789h 107.494ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.45 95.40 97.17 100.00 100.00 98.27 98.48 99.85

Past Results