HMAC Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 15.810s 5.294ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.880s 133.294us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.960s 57.648us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 13.940s 499.836us 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 7.500s 313.461us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 36.499m 226.180ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.960s 57.648us 20 20 100.00
hmac_csr_aliasing 7.500s 313.461us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 4.171m 26.581ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.763m 3.969ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 10.184m 186.765ms 5 5 100.00
hmac_test_sha384_vectors 46.946m 541.683ms 5 5 100.00
hmac_test_sha512_vectors 46.063m 213.370ms 5 5 100.00
hmac_test_hmac256_vectors 1.315m 16.285ms 5 5 100.00
hmac_test_hmac384_vectors 1.822m 9.902ms 5 5 100.00
hmac_test_hmac512_vectors 2.183m 16.639ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.150m 1.276ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 29.242m 8.324ms 50 50 100.00
V2 error hmac_error 4.572m 209.450ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.394m 32.188ms 50 50 100.00
V2 save_and_restore hmac_smoke 15.810s 5.294ms 50 50 100.00
hmac_long_msg 4.171m 26.581ms 50 50 100.00
hmac_back_pressure 1.763m 3.969ms 50 50 100.00
hmac_datapath_stress 29.242m 8.324ms 50 50 100.00
hmac_burst_wr 1.150m 1.276ms 50 50 100.00
hmac_stress_all 1.095h 149.501ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 15.810s 5.294ms 50 50 100.00
hmac_long_msg 4.171m 26.581ms 50 50 100.00
hmac_back_pressure 1.763m 3.969ms 50 50 100.00
hmac_datapath_stress 29.242m 8.324ms 50 50 100.00
hmac_wipe_secret 2.394m 32.188ms 50 50 100.00
hmac_test_sha256_vectors 10.184m 186.765ms 5 5 100.00
hmac_test_sha384_vectors 46.946m 541.683ms 5 5 100.00
hmac_test_sha512_vectors 46.063m 213.370ms 5 5 100.00
hmac_test_hmac256_vectors 1.315m 16.285ms 5 5 100.00
hmac_test_hmac384_vectors 1.822m 9.902ms 5 5 100.00
hmac_test_hmac512_vectors 2.183m 16.639ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 15.810s 5.294ms 50 50 100.00
hmac_long_msg 4.171m 26.581ms 50 50 100.00
hmac_back_pressure 1.763m 3.969ms 50 50 100.00
hmac_datapath_stress 29.242m 8.324ms 50 50 100.00
hmac_burst_wr 1.150m 1.276ms 50 50 100.00
hmac_error 4.572m 209.450ms 50 50 100.00
hmac_wipe_secret 2.394m 32.188ms 50 50 100.00
hmac_test_sha256_vectors 10.184m 186.765ms 5 5 100.00
hmac_test_sha384_vectors 46.946m 541.683ms 5 5 100.00
hmac_test_sha512_vectors 46.063m 213.370ms 5 5 100.00
hmac_test_hmac256_vectors 1.315m 16.285ms 5 5 100.00
hmac_test_hmac384_vectors 1.822m 9.902ms 5 5 100.00
hmac_test_hmac512_vectors 2.183m 16.639ms 5 5 100.00
hmac_stress_all 1.095h 149.501ms 50 50 100.00
V2 stress_all hmac_stress_all 1.095h 149.501ms 50 50 100.00
V2 alert_test hmac_alert_test 0.660s 33.122us 50 50 100.00
V2 intr_test hmac_intr_test 0.680s 15.327us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.790s 231.446us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.790s 231.446us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.880s 133.294us 5 5 100.00
hmac_csr_rw 0.960s 57.648us 20 20 100.00
hmac_csr_aliasing 7.500s 313.461us 5 5 100.00
hmac_same_csr_outstanding 2.410s 153.331us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.880s 133.294us 5 5 100.00
hmac_csr_rw 0.960s 57.648us 20 20 100.00
hmac_csr_aliasing 7.500s 313.461us 5 5 100.00
hmac_same_csr_outstanding 2.410s 153.331us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.010s 81.367us 5 5 100.00
hmac_tl_intg_err 4.550s 1.172ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.550s 1.172ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 15.810s 5.294ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.917h 103.432ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85

Past Results