HMAC Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.380s	1.225ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.990s	19.777us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.960s	417.838us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.070s	4.360ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.370s	2.369ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	11.054m	50.802ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.960s	417.838us	20	20	100.00
		hmac_csr_aliasing	9.370s	2.369ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.910m	18.038ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.780m	7.429ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.452m	140.683ms	5	5	100.00
		hmac_test_sha384_vectors	43.455m	770.887ms	5	5	100.00
		hmac_test_sha512_vectors	44.914m	217.780ms	5	5	100.00
		hmac_test_hmac256_vectors	1.145m	3.301ms	5	5	100.00
		hmac_test_hmac384_vectors	1.863m	21.933ms	5	5	100.00
		hmac_test_hmac512_vectors	2.165m	46.115ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.382m	27.911ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	28.747m	16.084ms	50	50	100.00
V2	error	hmac_error	3.545m	7.586ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.435m	124.422ms	50	50	100.00
V2	save_and_restore	hmac_smoke	15.380s	1.225ms	50	50	100.00
		hmac_long_msg	3.910m	18.038ms	50	50	100.00
		hmac_back_pressure	1.780m	7.429ms	50	50	100.00
		hmac_datapath_stress	28.747m	16.084ms	50	50	100.00
		hmac_burst_wr	1.382m	27.911ms	49	50	98.00
		hmac_stress_all	1.308h	480.337ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.380s	1.225ms	50	50	100.00
		hmac_long_msg	3.910m	18.038ms	50	50	100.00
		hmac_back_pressure	1.780m	7.429ms	50	50	100.00
		hmac_datapath_stress	28.747m	16.084ms	50	50	100.00
		hmac_wipe_secret	2.435m	124.422ms	50	50	100.00
		hmac_test_sha256_vectors	11.452m	140.683ms	5	5	100.00
		hmac_test_sha384_vectors	43.455m	770.887ms	5	5	100.00
		hmac_test_sha512_vectors	44.914m	217.780ms	5	5	100.00
		hmac_test_hmac256_vectors	1.145m	3.301ms	5	5	100.00
		hmac_test_hmac384_vectors	1.863m	21.933ms	5	5	100.00
		hmac_test_hmac512_vectors	2.165m	46.115ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.380s	1.225ms	50	50	100.00
		hmac_long_msg	3.910m	18.038ms	50	50	100.00
		hmac_back_pressure	1.780m	7.429ms	50	50	100.00
		hmac_datapath_stress	28.747m	16.084ms	50	50	100.00
		hmac_burst_wr	1.382m	27.911ms	49	50	98.00
		hmac_error	3.545m	7.586ms	50	50	100.00
		hmac_wipe_secret	2.435m	124.422ms	50	50	100.00
		hmac_test_sha256_vectors	11.452m	140.683ms	5	5	100.00
		hmac_test_sha384_vectors	43.455m	770.887ms	5	5	100.00
		hmac_test_sha512_vectors	44.914m	217.780ms	5	5	100.00
		hmac_test_hmac256_vectors	1.145m	3.301ms	5	5	100.00
		hmac_test_hmac384_vectors	1.863m	21.933ms	5	5	100.00
		hmac_test_hmac512_vectors	2.165m	46.115ms	5	5	100.00
		hmac_stress_all	1.308h	480.337ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.308h	480.337ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	14.007us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	14.340us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.710s	253.650us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.710s	253.650us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.990s	19.777us	5	5	100.00
		hmac_csr_rw	0.960s	417.838us	20	20	100.00
		hmac_csr_aliasing	9.370s	2.369ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	1.350ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.990s	19.777us	5	5	100.00
		hmac_csr_rw	0.960s	417.838us	20	20	100.00
		hmac_csr_aliasing	9.370s	2.369ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	1.350ms	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.080s	100.919us	5	5	100.00
		hmac_tl_intg_err	4.520s	268.463us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.520s	268.463us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.380s	1.225ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.260m	6.987ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			655	660	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	95.40	97.22	100.00	100.00	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 0.hmac_stress_all_with_rand_reset.35709838280445569453363933739730390618698709812490263825259817063760826665235
      Line 21370, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13232403899 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 13232403899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 2.hmac_stress_all_with_rand_reset.102657380215132284990643702188775758760057595011657898063640847320893480710993
      Line 10335, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1103068750 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1103068750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 7.hmac_stress_all_with_rand_reset.95036122639098101455147203935265439953286065932641297106259016987335148444423
      Line 34803, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19481576416 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 19481576416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 8.hmac_stress_all_with_rand_reset.29972040692406800106371943826735660434609430132400740268073723808056955785645
      Line 10832, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6911206882 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6911206882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_burst_wr has 1 failures.

    • 47.hmac_burst_wr.12298694347346382634763381901284651883866051910166351066407854717783295715623
      Line 629, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 2184180004 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 2184180004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• lint
• 2024.08.12_08.24.39
• 2024.08.11_08.10.28
• 2024.08.10_08.13.05
• 2024.08.09_07.45.18
• 2024.08.08_08.56.48
• 2024.08.07_08.49.36