HMAC Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.030s	1.419ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.050s	34.419us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	44.960us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.670s	3.270ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.820s	227.844us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.270m	53.774ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	44.960us	20	20	100.00
		hmac_csr_aliasing	7.820s	227.844us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.238m	10.987ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.707m	7.352ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.604m	88.509ms	5	5	100.00
		hmac_test_sha384_vectors	47.825m	309.286ms	5	5	100.00
		hmac_test_sha512_vectors	42.374m	174.624ms	5	5	100.00
		hmac_test_hmac256_vectors	1.235m	19.559ms	5	5	100.00
		hmac_test_hmac384_vectors	1.713m	4.882ms	5	5	100.00
		hmac_test_hmac512_vectors	2.177m	55.682ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.307m	9.116ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	32.918m	13.783ms	50	50	100.00
V2	error	hmac_error	3.869m	33.273ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.511m	14.278ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.030s	1.419ms	50	50	100.00
		hmac_long_msg	3.238m	10.987ms	50	50	100.00
		hmac_back_pressure	1.707m	7.352ms	50	50	100.00
		hmac_datapath_stress	32.918m	13.783ms	50	50	100.00
		hmac_burst_wr	1.307m	9.116ms	50	50	100.00
		hmac_stress_all	1.935h	333.694ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.030s	1.419ms	50	50	100.00
		hmac_long_msg	3.238m	10.987ms	50	50	100.00
		hmac_back_pressure	1.707m	7.352ms	50	50	100.00
		hmac_datapath_stress	32.918m	13.783ms	50	50	100.00
		hmac_wipe_secret	2.511m	14.278ms	50	50	100.00
		hmac_test_sha256_vectors	10.604m	88.509ms	5	5	100.00
		hmac_test_sha384_vectors	47.825m	309.286ms	5	5	100.00
		hmac_test_sha512_vectors	42.374m	174.624ms	5	5	100.00
		hmac_test_hmac256_vectors	1.235m	19.559ms	5	5	100.00
		hmac_test_hmac384_vectors	1.713m	4.882ms	5	5	100.00
		hmac_test_hmac512_vectors	2.177m	55.682ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.030s	1.419ms	50	50	100.00
		hmac_long_msg	3.238m	10.987ms	50	50	100.00
		hmac_back_pressure	1.707m	7.352ms	50	50	100.00
		hmac_datapath_stress	32.918m	13.783ms	50	50	100.00
		hmac_burst_wr	1.307m	9.116ms	50	50	100.00
		hmac_error	3.869m	33.273ms	50	50	100.00
		hmac_wipe_secret	2.511m	14.278ms	50	50	100.00
		hmac_test_sha256_vectors	10.604m	88.509ms	5	5	100.00
		hmac_test_sha384_vectors	47.825m	309.286ms	5	5	100.00
		hmac_test_sha512_vectors	42.374m	174.624ms	5	5	100.00
		hmac_test_hmac256_vectors	1.235m	19.559ms	5	5	100.00
		hmac_test_hmac384_vectors	1.713m	4.882ms	5	5	100.00
		hmac_test_hmac512_vectors	2.177m	55.682ms	5	5	100.00
		hmac_stress_all	1.935h	333.694ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.935h	333.694ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.670s	29.302us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	27.690us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.010s	184.958us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.010s	184.958us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.050s	34.419us	5	5	100.00
		hmac_csr_rw	0.980s	44.960us	20	20	100.00
		hmac_csr_aliasing	7.820s	227.844us	5	5	100.00
		hmac_same_csr_outstanding	2.490s	414.920us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.050s	34.419us	5	5	100.00
		hmac_csr_rw	0.980s	44.960us	20	20	100.00
		hmac_csr_aliasing	7.820s	227.844us	5	5	100.00
		hmac_same_csr_outstanding	2.490s	414.920us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.020s	324.079us	5	5	100.00
		hmac_tl_intg_err	4.650s	464.047us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.650s	464.047us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.030s	1.419ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.557m	26.477ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			656	660	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.11	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 2.hmac_stress_all_with_rand_reset.50137718212529458093890268432036893881721916430145661069749074293950074877432
    Line 12004, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16811088277 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16811088277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.hmac_stress_all_with_rand_reset.77258567448671379280429515184060057751373989115960848026934798659391214767016
    Line 1705, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7336209485 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7336209485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.51780360532075370962138732742462430353832005274599535426439287782314630429659
    Line 1714, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3153089150 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3153089150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 9.hmac_stress_all_with_rand_reset.59349290263836919614844980046425929385870494445135822511210402631151317936549
    Line 259, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28511360 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  28511360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `098010d125`