HMAC Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.840s	4.995ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	146.275us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.990s	31.813us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.540s	1.411ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.860s	303.641us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	20.173m	254.056ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.990s	31.813us	20	20	100.00
		hmac_csr_aliasing	5.860s	303.641us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.512m	48.636ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.822m	7.196ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.819m	105.014ms	5	5	100.00
		hmac_test_sha384_vectors	42.070m	278.443ms	5	5	100.00
		hmac_test_sha512_vectors	41.578m	796.205ms	5	5	100.00
		hmac_test_hmac256_vectors	1.304m	9.414ms	5	5	100.00
		hmac_test_hmac384_vectors	1.844m	19.830ms	5	5	100.00
		hmac_test_hmac512_vectors	2.194m	11.914ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.202m	13.459ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	37.402m	130.411ms	50	50	100.00
V2	error	hmac_error	4.075m	14.558ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.530m	25.149ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.840s	4.995ms	50	50	100.00
		hmac_long_msg	3.512m	48.636ms	50	50	100.00
		hmac_back_pressure	1.822m	7.196ms	50	50	100.00
		hmac_datapath_stress	37.402m	130.411ms	50	50	100.00
		hmac_burst_wr	1.202m	13.459ms	50	50	100.00
		hmac_stress_all	1.987h	87.079ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.840s	4.995ms	50	50	100.00
		hmac_long_msg	3.512m	48.636ms	50	50	100.00
		hmac_back_pressure	1.822m	7.196ms	50	50	100.00
		hmac_datapath_stress	37.402m	130.411ms	50	50	100.00
		hmac_wipe_secret	2.530m	25.149ms	50	50	100.00
		hmac_test_sha256_vectors	10.819m	105.014ms	5	5	100.00
		hmac_test_sha384_vectors	42.070m	278.443ms	5	5	100.00
		hmac_test_sha512_vectors	41.578m	796.205ms	5	5	100.00
		hmac_test_hmac256_vectors	1.304m	9.414ms	5	5	100.00
		hmac_test_hmac384_vectors	1.844m	19.830ms	5	5	100.00
		hmac_test_hmac512_vectors	2.194m	11.914ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.840s	4.995ms	50	50	100.00
		hmac_long_msg	3.512m	48.636ms	50	50	100.00
		hmac_back_pressure	1.822m	7.196ms	50	50	100.00
		hmac_datapath_stress	37.402m	130.411ms	50	50	100.00
		hmac_burst_wr	1.202m	13.459ms	50	50	100.00
		hmac_error	4.075m	14.558ms	50	50	100.00
		hmac_wipe_secret	2.530m	25.149ms	50	50	100.00
		hmac_test_sha256_vectors	10.819m	105.014ms	5	5	100.00
		hmac_test_sha384_vectors	42.070m	278.443ms	5	5	100.00
		hmac_test_sha512_vectors	41.578m	796.205ms	5	5	100.00
		hmac_test_hmac256_vectors	1.304m	9.414ms	5	5	100.00
		hmac_test_hmac384_vectors	1.844m	19.830ms	5	5	100.00
		hmac_test_hmac512_vectors	2.194m	11.914ms	5	5	100.00
		hmac_stress_all	1.987h	87.079ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.987h	87.079ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	14.810us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	14.168us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.170s	887.048us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.170s	887.048us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	146.275us	5	5	100.00
		hmac_csr_rw	0.990s	31.813us	20	20	100.00
		hmac_csr_aliasing	5.860s	303.641us	5	5	100.00
		hmac_same_csr_outstanding	2.440s	825.811us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	146.275us	5	5	100.00
		hmac_csr_rw	0.990s	31.813us	20	20	100.00
		hmac_csr_aliasing	5.860s	303.641us	5	5	100.00
		hmac_same_csr_outstanding	2.440s	825.811us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.030s	457.436us	5	5	100.00
		hmac_tl_intg_err	4.840s	1.172ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.840s	1.172ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.840s	4.995ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	16.307m	109.739ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			653	660	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.45	95.40	97.17	100.00	100.00	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 4.hmac_stress_all_with_rand_reset.21238780380775900852211971137537396522958209566227970301993598863100779322487
      Line 4060, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12415876927 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 12415876927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.hmac_stress_all_with_rand_reset.73440496761149860023138396030450109360966712116507171463255616346396220679817
      Line 1114, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 365251098 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 365251098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 7.hmac_stress_all_with_rand_reset.33448034475028381958947455989520930277271476021432962912624925423065102602139
      Line 285, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  39657718 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @  39657718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.hmac_stress_all_with_rand_reset.107658384823251140266187949344783029812625875257514725214473725754483530249757
      Line 23117, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30231305416 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 30231305416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 0.hmac_stress_all_with_rand_reset.105739991990687566729930037541133394360924166654718420727747468952156764866801
      Line 4122, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2355843453 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2355843453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 2.hmac_stress_all_with_rand_reset.82634207940962602687376136307913769994102234691534822673784037717159648034040
      Line 2381, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3499173866 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3499173866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 5.hmac_stress_all_with_rand_reset.20869764807572881569418793199130437233639071550804941732762614243952849856965
      Line 16183, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33018021104 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 33018021104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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