HMAC Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	19.380s	6.239ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.940s	64.291us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.950s	105.326us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.680s	3.803ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.080s	322.538us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	15.034m	249.920ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.950s	105.326us	20	20	100.00
		hmac_csr_aliasing	8.080s	322.538us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.606m	57.426ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.792m	1.951ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.114m	115.318ms	5	5	100.00
		hmac_test_sha384_vectors	42.272m	919.439ms	5	5	100.00
		hmac_test_sha512_vectors	41.072m	807.789ms	5	5	100.00
		hmac_test_hmac256_vectors	1.295m	14.056ms	5	5	100.00
		hmac_test_hmac384_vectors	1.543m	5.998ms	5	5	100.00
		hmac_test_hmac512_vectors	2.209m	22.120ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.355m	1.929ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	28.949m	16.538ms	50	50	100.00
V2	error	hmac_error	3.794m	50.672ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.327m	33.411ms	50	50	100.00
V2	save_and_restore	hmac_smoke	19.380s	6.239ms	50	50	100.00
		hmac_long_msg	4.606m	57.426ms	50	50	100.00
		hmac_back_pressure	1.792m	1.951ms	50	50	100.00
		hmac_datapath_stress	28.949m	16.538ms	50	50	100.00
		hmac_burst_wr	1.355m	1.929ms	50	50	100.00
		hmac_stress_all	1.298h	30.518ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	19.380s	6.239ms	50	50	100.00
		hmac_long_msg	4.606m	57.426ms	50	50	100.00
		hmac_back_pressure	1.792m	1.951ms	50	50	100.00
		hmac_datapath_stress	28.949m	16.538ms	50	50	100.00
		hmac_wipe_secret	2.327m	33.411ms	50	50	100.00
		hmac_test_sha256_vectors	11.114m	115.318ms	5	5	100.00
		hmac_test_sha384_vectors	42.272m	919.439ms	5	5	100.00
		hmac_test_sha512_vectors	41.072m	807.789ms	5	5	100.00
		hmac_test_hmac256_vectors	1.295m	14.056ms	5	5	100.00
		hmac_test_hmac384_vectors	1.543m	5.998ms	5	5	100.00
		hmac_test_hmac512_vectors	2.209m	22.120ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	19.380s	6.239ms	50	50	100.00
		hmac_long_msg	4.606m	57.426ms	50	50	100.00
		hmac_back_pressure	1.792m	1.951ms	50	50	100.00
		hmac_datapath_stress	28.949m	16.538ms	50	50	100.00
		hmac_burst_wr	1.355m	1.929ms	50	50	100.00
		hmac_error	3.794m	50.672ms	50	50	100.00
		hmac_wipe_secret	2.327m	33.411ms	50	50	100.00
		hmac_test_sha256_vectors	11.114m	115.318ms	5	5	100.00
		hmac_test_sha384_vectors	42.272m	919.439ms	5	5	100.00
		hmac_test_sha512_vectors	41.072m	807.789ms	5	5	100.00
		hmac_test_hmac256_vectors	1.295m	14.056ms	5	5	100.00
		hmac_test_hmac384_vectors	1.543m	5.998ms	5	5	100.00
		hmac_test_hmac512_vectors	2.209m	22.120ms	5	5	100.00
		hmac_stress_all	1.298h	30.518ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.298h	30.518ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.640s	14.266us	50	50	100.00
V2	intr_test	hmac_intr_test	0.800s	15.332us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.400s	1.367ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.400s	1.367ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.940s	64.291us	5	5	100.00
		hmac_csr_rw	0.950s	105.326us	20	20	100.00
		hmac_csr_aliasing	8.080s	322.538us	5	5	100.00
		hmac_same_csr_outstanding	2.450s	302.543us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.940s	64.291us	5	5	100.00
		hmac_csr_rw	0.950s	105.326us	20	20	100.00
		hmac_csr_aliasing	8.080s	322.538us	5	5	100.00
		hmac_same_csr_outstanding	2.450s	302.543us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	0.970s	81.948us	5	5	100.00
		hmac_tl_intg_err	4.720s	627.038us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.720s	627.038us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	19.380s	6.239ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	9.677m	12.186ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			654	660	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 2.hmac_stress_all_with_rand_reset.110886642544124799080282340598147532867758202856579695192326110967240653542187
      Line 9692, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8883802997 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 8883802997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.hmac_stress_all_with_rand_reset.71144126303038024046327960405927258215194766272486954325604861235593746041277
      Line 11328, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24279822638 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 24279822638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 0.hmac_stress_all_with_rand_reset.70904923281413821891270981267621269533823903648860134400635598741955215858443
      Line 590, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 184558249 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 184558249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 1.hmac_stress_all_with_rand_reset.106447497801745916774919422745963889464672926447369994292484491830253322230466
      Line 29235, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60111297264 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 60111297264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 5.hmac_stress_all_with_rand_reset.57956773484516519207817645597496147086527782940742154291898171795006240718612
      Line 10510, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2870376761 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2870376761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_stress_all has 1 failures.

    • 10.hmac_stress_all.59329662691352007251782795444658576087968915356932499882717002749427511032551
      Line 276, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest/run.log

        UVM_ERROR @ 117947621 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 117947621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.08.13_07.54.12
• 2024.08.12_08.24.39
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