HMAC Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.020s	1.171ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.930s	35.737us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.930s	119.347us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.440s	1.581ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.040s	4.606ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.442m	122.618ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.930s	119.347us	20	20	100.00
		hmac_csr_aliasing	9.040s	4.606ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.751m	17.311ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.881m	8.167ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.045m	203.426ms	5	5	100.00
		hmac_test_sha384_vectors	45.639m	209.866ms	5	5	100.00
		hmac_test_sha512_vectors	44.799m	799.322ms	5	5	100.00
		hmac_test_hmac256_vectors	1.322m	4.928ms	5	5	100.00
		hmac_test_hmac384_vectors	1.675m	53.602ms	5	5	100.00
		hmac_test_hmac512_vectors	2.045m	13.278ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.271m	10.462ms	48	50	96.00
V2	datapath_stress	hmac_datapath_stress	26.208m	14.819ms	50	50	100.00
V2	error	hmac_error	5.017m	39.859ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.438m	75.203ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.020s	1.171ms	50	50	100.00
		hmac_long_msg	3.751m	17.311ms	50	50	100.00
		hmac_back_pressure	1.881m	8.167ms	50	50	100.00
		hmac_datapath_stress	26.208m	14.819ms	50	50	100.00
		hmac_burst_wr	1.271m	10.462ms	48	50	96.00
		hmac_stress_all	1.417h	36.196ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.020s	1.171ms	50	50	100.00
		hmac_long_msg	3.751m	17.311ms	50	50	100.00
		hmac_back_pressure	1.881m	8.167ms	50	50	100.00
		hmac_datapath_stress	26.208m	14.819ms	50	50	100.00
		hmac_wipe_secret	2.438m	75.203ms	50	50	100.00
		hmac_test_sha256_vectors	11.045m	203.426ms	5	5	100.00
		hmac_test_sha384_vectors	45.639m	209.866ms	5	5	100.00
		hmac_test_sha512_vectors	44.799m	799.322ms	5	5	100.00
		hmac_test_hmac256_vectors	1.322m	4.928ms	5	5	100.00
		hmac_test_hmac384_vectors	1.675m	53.602ms	5	5	100.00
		hmac_test_hmac512_vectors	2.045m	13.278ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.020s	1.171ms	50	50	100.00
		hmac_long_msg	3.751m	17.311ms	50	50	100.00
		hmac_back_pressure	1.881m	8.167ms	50	50	100.00
		hmac_datapath_stress	26.208m	14.819ms	50	50	100.00
		hmac_burst_wr	1.271m	10.462ms	48	50	96.00
		hmac_error	5.017m	39.859ms	50	50	100.00
		hmac_wipe_secret	2.438m	75.203ms	50	50	100.00
		hmac_test_sha256_vectors	11.045m	203.426ms	5	5	100.00
		hmac_test_sha384_vectors	45.639m	209.866ms	5	5	100.00
		hmac_test_sha512_vectors	44.799m	799.322ms	5	5	100.00
		hmac_test_hmac256_vectors	1.322m	4.928ms	5	5	100.00
		hmac_test_hmac384_vectors	1.675m	53.602ms	5	5	100.00
		hmac_test_hmac512_vectors	2.045m	13.278ms	5	5	100.00
		hmac_stress_all	1.417h	36.196ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.417h	36.196ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	22.199us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	55.345us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.530s	3.248ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.530s	3.248ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.930s	35.737us	5	5	100.00
		hmac_csr_rw	0.930s	119.347us	20	20	100.00
		hmac_csr_aliasing	9.040s	4.606ms	5	5	100.00
		hmac_same_csr_outstanding	2.350s	473.146us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.930s	35.737us	5	5	100.00
		hmac_csr_rw	0.930s	119.347us	20	20	100.00
		hmac_csr_aliasing	9.040s	4.606ms	5	5	100.00
		hmac_same_csr_outstanding	2.350s	473.146us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	0.970s	352.991us	5	5	100.00
		hmac_tl_intg_err	4.470s	1.155ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.470s	1.155ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.020s	1.171ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	9.512m	8.138ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			654	660	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	95.40	97.27	100.00	100.00	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 1.hmac_stress_all_with_rand_reset.19346658791886061385608795369886622926677032252800624113225774619536496698990
    Line 19056, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25424479493 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25424479493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.hmac_stress_all_with_rand_reset.92056876476056924120257927052358627214266684701849060086837944316455506411001
    Line 15654, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1806079192 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1806079192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:
- Test hmac_burst_wr has 2 failures.
  - 10.hmac_burst_wr.27215675522559967870325984514808394116505631165594791727072521727335844412409
    Line 740, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 426814380 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 426814380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.hmac_burst_wr.41625751937346288138871608176331921704914320241398212762511910250069795021560
    Line 489, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 1050680380 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 1050680380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 2.hmac_stress_all_with_rand_reset.32882295760200350190362127462358331030841794259384414274336967069980367867544
    Line 12629, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17843341759 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 17843341759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 8.hmac_stress_all_with_rand_reset.58471862658565053877007633222795225334428708099784736910754112382604299365343
    Line 30348, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21252812761 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 21252812761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`