HMAC Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.940s	962.076us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.060s	66.615us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	31.213us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.930s	1.853ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.200s	221.705us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.289m	85.938ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	31.213us	20	20	100.00
		hmac_csr_aliasing	8.200s	221.705us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.604m	66.884ms	49	50	98.00
V2	back_pressure	hmac_back_pressure	1.843m	8.682ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.829m	904.607ms	4	5	80.00
		hmac_test_sha384_vectors	43.083m	586.724ms	5	5	100.00
		hmac_test_sha512_vectors	41.299m	277.768ms	5	5	100.00
		hmac_test_hmac256_vectors	1.315m	19.579ms	5	5	100.00
		hmac_test_hmac384_vectors	1.680m	9.949ms	5	5	100.00
		hmac_test_hmac512_vectors	2.354m	16.985ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.257m	22.224ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	23.470m	20.908ms	50	50	100.00
V2	error	hmac_error	4.276m	9.487ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.667m	21.945ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.940s	962.076us	50	50	100.00
		hmac_long_msg	3.604m	66.884ms	49	50	98.00
		hmac_back_pressure	1.843m	8.682ms	50	50	100.00
		hmac_datapath_stress	23.470m	20.908ms	50	50	100.00
		hmac_burst_wr	1.257m	22.224ms	50	50	100.00
		hmac_stress_all	1.251h	177.641ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.940s	962.076us	50	50	100.00
		hmac_long_msg	3.604m	66.884ms	49	50	98.00
		hmac_back_pressure	1.843m	8.682ms	50	50	100.00
		hmac_datapath_stress	23.470m	20.908ms	50	50	100.00
		hmac_wipe_secret	2.667m	21.945ms	50	50	100.00
		hmac_test_sha256_vectors	11.829m	904.607ms	4	5	80.00
		hmac_test_sha384_vectors	43.083m	586.724ms	5	5	100.00
		hmac_test_sha512_vectors	41.299m	277.768ms	5	5	100.00
		hmac_test_hmac256_vectors	1.315m	19.579ms	5	5	100.00
		hmac_test_hmac384_vectors	1.680m	9.949ms	5	5	100.00
		hmac_test_hmac512_vectors	2.354m	16.985ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.940s	962.076us	50	50	100.00
		hmac_long_msg	3.604m	66.884ms	49	50	98.00
		hmac_back_pressure	1.843m	8.682ms	50	50	100.00
		hmac_datapath_stress	23.470m	20.908ms	50	50	100.00
		hmac_burst_wr	1.257m	22.224ms	50	50	100.00
		hmac_error	4.276m	9.487ms	50	50	100.00
		hmac_wipe_secret	2.667m	21.945ms	50	50	100.00
		hmac_test_sha256_vectors	11.829m	904.607ms	4	5	80.00
		hmac_test_sha384_vectors	43.083m	586.724ms	5	5	100.00
		hmac_test_sha512_vectors	41.299m	277.768ms	5	5	100.00
		hmac_test_hmac256_vectors	1.315m	19.579ms	5	5	100.00
		hmac_test_hmac384_vectors	1.680m	9.949ms	5	5	100.00
		hmac_test_hmac512_vectors	2.354m	16.985ms	5	5	100.00
		hmac_stress_all	1.251h	177.641ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.251h	177.641ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	54.937us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	43.975us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.480s	248.500us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.480s	248.500us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.060s	66.615us	5	5	100.00
		hmac_csr_rw	1.000s	31.213us	20	20	100.00
		hmac_csr_aliasing	8.200s	221.705us	5	5	100.00
		hmac_same_csr_outstanding	2.300s	44.229us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.060s	66.615us	5	5	100.00
		hmac_csr_rw	1.000s	31.213us	20	20	100.00
		hmac_csr_aliasing	8.200s	221.705us	5	5	100.00
		hmac_same_csr_outstanding	2.300s	44.229us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.000s	1.048ms	5	5	100.00
		hmac_tl_intg_err	4.810s	322.057us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.810s	322.057us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.940s	962.076us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.588m	14.409ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			651	660	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test hmac_test_sha256_vectors has 1 failures.

    • 1.hmac_test_sha256_vectors.92626821618383804892623274144874486921148434888905042820485507848650680360976
      Line 75291, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_long_msg has 1 failures.

    • 16.hmac_long_msg.19923813530351690542825214326026681140974404583831763648666570820308817555561
      Line 33184, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_long_msg/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 1.hmac_stress_all_with_rand_reset.94829592887329325907140755160267555314647888879197480932161510139796716844604
      Line 22029, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39974971943 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 39974971943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.hmac_stress_all_with_rand_reset.114631047270547124707603307067963507321798277783296583910944933655312549882400
      Line 8879, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17018115533 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 17018115533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 2.hmac_stress_all_with_rand_reset.9927201260160854520981856966640836168141461226020942611932782527414651963820
      Line 9816, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42793971693 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 42793971693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 3.hmac_stress_all_with_rand_reset.45427838572386424717699011566278899895807274787375838281396267201526368233086
      Line 24618, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48497608823 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 48497608823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 5.hmac_stress_all_with_rand_reset.114373821283211831390010268553934792537772118965611786948796926519938740292629
      Line 9299, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4831550781 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4831550781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 6.hmac_stress_all_with_rand_reset.55189975126063999872398456504137231831822836425003211644875207230493905971914
      Line 23887, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9962200459 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 9962200459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 8.hmac_stress_all_with_rand_reset.104648240218595560790187386521756858323213313325699010403257774593268929474058
      Line 262, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  28154019 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @  28154019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.08.17_07.06.43
• 2024.08.16_08.29.14
• 2024.08.15_05.21.39
• 2024.08.14_08.25.10
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• 2024.08.12_08.24.39