HMAC Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.180s	4.313ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.980s	187.644us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.950s	47.853us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.790s	1.642ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.520s	1.997ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	10.577m	176.513ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.950s	47.853us	20	20	100.00
		hmac_csr_aliasing	8.520s	1.997ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.553m	11.582ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.778m	10.075ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.870m	47.638ms	5	5	100.00
		hmac_test_sha384_vectors	48.013m	426.414ms	5	5	100.00
		hmac_test_sha512_vectors	45.259m	45.086ms	5	5	100.00
		hmac_test_hmac256_vectors	1.132m	25.351ms	5	5	100.00
		hmac_test_hmac384_vectors	1.883m	32.388ms	5	5	100.00
		hmac_test_hmac512_vectors	2.338m	10.805ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.234m	6.327ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	36.440m	18.687ms	50	50	100.00
V2	error	hmac_error	4.586m	39.762ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.557m	126.485ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.180s	4.313ms	50	50	100.00
		hmac_long_msg	3.553m	11.582ms	50	50	100.00
		hmac_back_pressure	1.778m	10.075ms	50	50	100.00
		hmac_datapath_stress	36.440m	18.687ms	50	50	100.00
		hmac_burst_wr	1.234m	6.327ms	50	50	100.00
		hmac_stress_all	1.022h	1.404s	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.180s	4.313ms	50	50	100.00
		hmac_long_msg	3.553m	11.582ms	50	50	100.00
		hmac_back_pressure	1.778m	10.075ms	50	50	100.00
		hmac_datapath_stress	36.440m	18.687ms	50	50	100.00
		hmac_wipe_secret	2.557m	126.485ms	50	50	100.00
		hmac_test_sha256_vectors	10.870m	47.638ms	5	5	100.00
		hmac_test_sha384_vectors	48.013m	426.414ms	5	5	100.00
		hmac_test_sha512_vectors	45.259m	45.086ms	5	5	100.00
		hmac_test_hmac256_vectors	1.132m	25.351ms	5	5	100.00
		hmac_test_hmac384_vectors	1.883m	32.388ms	5	5	100.00
		hmac_test_hmac512_vectors	2.338m	10.805ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.180s	4.313ms	50	50	100.00
		hmac_long_msg	3.553m	11.582ms	50	50	100.00
		hmac_back_pressure	1.778m	10.075ms	50	50	100.00
		hmac_datapath_stress	36.440m	18.687ms	50	50	100.00
		hmac_burst_wr	1.234m	6.327ms	50	50	100.00
		hmac_error	4.586m	39.762ms	50	50	100.00
		hmac_wipe_secret	2.557m	126.485ms	50	50	100.00
		hmac_test_sha256_vectors	10.870m	47.638ms	5	5	100.00
		hmac_test_sha384_vectors	48.013m	426.414ms	5	5	100.00
		hmac_test_sha512_vectors	45.259m	45.086ms	5	5	100.00
		hmac_test_hmac256_vectors	1.132m	25.351ms	5	5	100.00
		hmac_test_hmac384_vectors	1.883m	32.388ms	5	5	100.00
		hmac_test_hmac512_vectors	2.338m	10.805ms	5	5	100.00
		hmac_stress_all	1.022h	1.404s	49	50	98.00
V2	stress_all	hmac_stress_all	1.022h	1.404s	49	50	98.00
V2	alert_test	hmac_alert_test	0.670s	60.351us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	29.698us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.220s	470.472us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.220s	470.472us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.980s	187.644us	5	5	100.00
		hmac_csr_rw	0.950s	47.853us	20	20	100.00
		hmac_csr_aliasing	8.520s	1.997ms	5	5	100.00
		hmac_same_csr_outstanding	2.270s	111.223us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.980s	187.644us	5	5	100.00
		hmac_csr_rw	0.950s	47.853us	20	20	100.00
		hmac_csr_aliasing	8.520s	1.997ms	5	5	100.00
		hmac_same_csr_outstanding	2.270s	111.223us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.000s	322.189us	5	5	100.00
		hmac_tl_intg_err	4.430s	222.368us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.430s	222.368us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.180s	4.313ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	15.272m	6.478ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			653	660	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	95.26	97.22	100.00	97.06	98.12	97.97	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 0.hmac_stress_all_with_rand_reset.22557076145219773557135632405258479799279338921288572890968025877117543521640
      Line 262, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 222906167 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 222906167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.hmac_stress_all_with_rand_reset.15421846895561150002347490255635504667484700683143190773645809252121759145816
      Line 24552, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2708987486 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2708987486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 2.hmac_stress_all_with_rand_reset.113822437901679659236735081821368545858508233369963447455905315573071138890243
      Line 15070, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3998829900 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 3998829900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_stress_all has 1 failures.

    • 3.hmac_stress_all.415982935516322438978539375836735828464016742867117744850376032365187860443
      Line 3412, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log

        UVM_ERROR @ 850253566 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 850253566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 1.hmac_stress_all_with_rand_reset.19712564584087650320126688171304556543349186704004253981202151394833047664774
      Line 68479, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6478126719 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6478126719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 3.hmac_stress_all_with_rand_reset.44682077826208342258325317657736850487314385804842530732668804949142427741358
      Line 13009, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3927466166 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3927466166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 7.hmac_stress_all_with_rand_reset.1407464138827514620904166376794402670546585607062813569570470526961276349554
      Line 6440, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8248668814 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 8248668814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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