HMAC Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.440s	1.201ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.040s	148.994us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	117.837us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.820s	7.506ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.490s	2.498ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.012m	120.969ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	117.837us	20	20	100.00
		hmac_csr_aliasing	8.490s	2.498ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.094m	64.054ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.909m	7.860ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.687m	37.676ms	5	5	100.00
		hmac_test_sha384_vectors	44.913m	228.027ms	5	5	100.00
		hmac_test_sha512_vectors	44.406m	207.469ms	5	5	100.00
		hmac_test_hmac256_vectors	1.380m	43.128ms	5	5	100.00
		hmac_test_hmac384_vectors	1.808m	27.184ms	5	5	100.00
		hmac_test_hmac512_vectors	2.193m	32.106ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.291m	16.999ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.131m	29.529ms	50	50	100.00
V2	error	hmac_error	4.564m	65.074ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.636m	100.796ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.440s	1.201ms	50	50	100.00
		hmac_long_msg	4.094m	64.054ms	50	50	100.00
		hmac_back_pressure	1.909m	7.860ms	50	50	100.00
		hmac_datapath_stress	26.131m	29.529ms	50	50	100.00
		hmac_burst_wr	1.291m	16.999ms	50	50	100.00
		hmac_stress_all	1.600h	106.294ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.440s	1.201ms	50	50	100.00
		hmac_long_msg	4.094m	64.054ms	50	50	100.00
		hmac_back_pressure	1.909m	7.860ms	50	50	100.00
		hmac_datapath_stress	26.131m	29.529ms	50	50	100.00
		hmac_wipe_secret	2.636m	100.796ms	50	50	100.00
		hmac_test_sha256_vectors	11.687m	37.676ms	5	5	100.00
		hmac_test_sha384_vectors	44.913m	228.027ms	5	5	100.00
		hmac_test_sha512_vectors	44.406m	207.469ms	5	5	100.00
		hmac_test_hmac256_vectors	1.380m	43.128ms	5	5	100.00
		hmac_test_hmac384_vectors	1.808m	27.184ms	5	5	100.00
		hmac_test_hmac512_vectors	2.193m	32.106ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.440s	1.201ms	50	50	100.00
		hmac_long_msg	4.094m	64.054ms	50	50	100.00
		hmac_back_pressure	1.909m	7.860ms	50	50	100.00
		hmac_datapath_stress	26.131m	29.529ms	50	50	100.00
		hmac_burst_wr	1.291m	16.999ms	50	50	100.00
		hmac_error	4.564m	65.074ms	50	50	100.00
		hmac_wipe_secret	2.636m	100.796ms	50	50	100.00
		hmac_test_sha256_vectors	11.687m	37.676ms	5	5	100.00
		hmac_test_sha384_vectors	44.913m	228.027ms	5	5	100.00
		hmac_test_sha512_vectors	44.406m	207.469ms	5	5	100.00
		hmac_test_hmac256_vectors	1.380m	43.128ms	5	5	100.00
		hmac_test_hmac384_vectors	1.808m	27.184ms	5	5	100.00
		hmac_test_hmac512_vectors	2.193m	32.106ms	5	5	100.00
		hmac_stress_all	1.600h	106.294ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.600h	106.294ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.650s	15.493us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	36.210us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.310s	243.212us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.310s	243.212us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.040s	148.994us	5	5	100.00
		hmac_csr_rw	1.000s	117.837us	20	20	100.00
		hmac_csr_aliasing	8.490s	2.498ms	5	5	100.00
		hmac_same_csr_outstanding	2.540s	146.698us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.040s	148.994us	5	5	100.00
		hmac_csr_rw	1.000s	117.837us	20	20	100.00
		hmac_csr_aliasing	8.490s	2.498ms	5	5	100.00
		hmac_same_csr_outstanding	2.540s	146.698us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.050s	330.695us	5	5	100.00
		hmac_tl_intg_err	4.630s	225.569us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.630s	225.569us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.440s	1.201ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	14.713m	36.271ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 2.hmac_stress_all_with_rand_reset.34456168455597145639577558416798990957791901607114554951637777839392427287122
    Line 27323, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102380296862 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 102380296862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 9.hmac_stress_all_with_rand_reset.51938497271476899638363123518975551922456557202787992710949621876217323410040
    Line 5448, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1745624003 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1745624003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
- Test hmac_stress_all has 1 failures.
  - 44.hmac_stress_all.85650017283947754802704989618266145550160982021092912566142009414794813285996
    Line 1294, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 811268659 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 811268659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e45ccd274a`