HMAC Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	21.300s	8.952ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.380s	71.658us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.380s	122.049us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	19.600s	1.277ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	12.850s	1.698ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	8.826m	91.129ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.380s	122.049us	20	20	100.00
		hmac_csr_aliasing	12.850s	1.698ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.891m	16.836ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.217m	1.748ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.696m	197.989ms	5	5	100.00
		hmac_test_sha384_vectors	43.610m	1.263s	5	5	100.00
		hmac_test_sha512_vectors	41.909m	265.991ms	5	5	100.00
		hmac_test_hmac256_vectors	1.468m	49.602ms	5	5	100.00
		hmac_test_hmac384_vectors	2.310m	35.077ms	5	5	100.00
		hmac_test_hmac512_vectors	2.688m	11.644ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.629m	5.851ms	48	50	96.00
V2	datapath_stress	hmac_datapath_stress	29.816m	34.946ms	50	50	100.00
V2	error	hmac_error	4.571m	40.444ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.006m	22.640ms	50	50	100.00
V2	save_and_restore	hmac_smoke	21.300s	8.952ms	50	50	100.00
		hmac_long_msg	4.891m	16.836ms	50	50	100.00
		hmac_back_pressure	2.217m	1.748ms	50	50	100.00
		hmac_datapath_stress	29.816m	34.946ms	50	50	100.00
		hmac_burst_wr	1.629m	5.851ms	48	50	96.00
		hmac_stress_all	56.391m	133.058ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	21.300s	8.952ms	50	50	100.00
		hmac_long_msg	4.891m	16.836ms	50	50	100.00
		hmac_back_pressure	2.217m	1.748ms	50	50	100.00
		hmac_datapath_stress	29.816m	34.946ms	50	50	100.00
		hmac_wipe_secret	3.006m	22.640ms	50	50	100.00
		hmac_test_sha256_vectors	10.696m	197.989ms	5	5	100.00
		hmac_test_sha384_vectors	43.610m	1.263s	5	5	100.00
		hmac_test_sha512_vectors	41.909m	265.991ms	5	5	100.00
		hmac_test_hmac256_vectors	1.468m	49.602ms	5	5	100.00
		hmac_test_hmac384_vectors	2.310m	35.077ms	5	5	100.00
		hmac_test_hmac512_vectors	2.688m	11.644ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	21.300s	8.952ms	50	50	100.00
		hmac_long_msg	4.891m	16.836ms	50	50	100.00
		hmac_back_pressure	2.217m	1.748ms	50	50	100.00
		hmac_datapath_stress	29.816m	34.946ms	50	50	100.00
		hmac_burst_wr	1.629m	5.851ms	48	50	96.00
		hmac_error	4.571m	40.444ms	50	50	100.00
		hmac_wipe_secret	3.006m	22.640ms	50	50	100.00
		hmac_test_sha256_vectors	10.696m	197.989ms	5	5	100.00
		hmac_test_sha384_vectors	43.610m	1.263s	5	5	100.00
		hmac_test_sha512_vectors	41.909m	265.991ms	5	5	100.00
		hmac_test_hmac256_vectors	1.468m	49.602ms	5	5	100.00
		hmac_test_hmac384_vectors	2.310m	35.077ms	5	5	100.00
		hmac_test_hmac512_vectors	2.688m	11.644ms	5	5	100.00
		hmac_stress_all	56.391m	133.058ms	50	50	100.00
V2	stress_all	hmac_stress_all	56.391m	133.058ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.940s	15.499us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	49.348us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	6.630s	236.785us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	6.630s	236.785us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.380s	71.658us	5	5	100.00
		hmac_csr_rw	1.380s	122.049us	20	20	100.00
		hmac_csr_aliasing	12.850s	1.698ms	5	5	100.00
		hmac_same_csr_outstanding	3.800s	262.515us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.380s	71.658us	5	5	100.00
		hmac_csr_rw	1.380s	122.049us	20	20	100.00
		hmac_csr_aliasing	12.850s	1.698ms	5	5	100.00
		hmac_same_csr_outstanding	3.800s	262.515us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.650s	157.033us	5	5	100.00
		hmac_tl_intg_err	6.410s	990.838us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.410s	990.838us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	21.300s	8.952ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.194m	7.452ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			654	660	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	95.40	97.17	100.00	94.12	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:
- Test hmac_burst_wr has 2 failures.
  - 1.hmac_burst_wr.19778513746085422450917561846223943763751498661658365297768312922887335738827
    Line 573, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/1.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 1292652484 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 1292652484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.hmac_burst_wr.95866231027090417917232555362506828549080852183425722964737577385316208117430
    Line 708, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/10.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 928134318 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 928134318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 3.hmac_stress_all_with_rand_reset.114041646110934257977390393981451046960427516636367547210056403168567246299210
    Line 5132, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3224520697 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3224520697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 4.hmac_stress_all_with_rand_reset.42671922175575050337127597756122216102425159090524021412641244619017302012921
    Line 69441, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7451850728 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7451850728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 5.hmac_stress_all_with_rand_reset.97006036963470470683280870565097249508751287797613220598479932352472260141340
    Line 8414, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4126467002 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4126467002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.37012744786564314903370975579875161291414528850527888835093078943145116485645
    Line 3203, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5686854906 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5686854906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `34b8fc33e3`