HMAC Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.950s	680.637us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.720s	24.198us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.880s	30.348us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.200s	5.470ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.000s	1.743ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	2.100s	511.194us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.880s	30.348us	20	20	100.00
		hmac_csr_aliasing	7.000s	1.743ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.031m	96.531ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.326m	1.584ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.830m	54.560ms	5	5	100.00
		hmac_test_sha384_vectors	38.916m	212.729ms	5	5	100.00
		hmac_test_sha512_vectors	37.320m	2.000s	5	5	100.00
		hmac_test_hmac256_vectors	1.176m	7.163ms	5	5	100.00
		hmac_test_hmac384_vectors	1.584m	19.391ms	5	5	100.00
		hmac_test_hmac512_vectors	1.898m	83.439ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	57.210s	6.165ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.337m	16.413ms	50	50	100.00
V2	error	hmac_error	4.240m	124.148ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.238m	36.220ms	50	50	100.00
V2	save_and_restore	hmac_smoke	13.950s	680.637us	50	50	100.00
		hmac_long_msg	3.031m	96.531ms	50	50	100.00
		hmac_back_pressure	1.326m	1.584ms	50	50	100.00
		hmac_datapath_stress	22.337m	16.413ms	50	50	100.00
		hmac_burst_wr	57.210s	6.165ms	50	50	100.00
		hmac_stress_all	56.221m	153.683ms	48	50	96.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.950s	680.637us	50	50	100.00
		hmac_long_msg	3.031m	96.531ms	50	50	100.00
		hmac_back_pressure	1.326m	1.584ms	50	50	100.00
		hmac_datapath_stress	22.337m	16.413ms	50	50	100.00
		hmac_wipe_secret	2.238m	36.220ms	50	50	100.00
		hmac_test_sha256_vectors	9.830m	54.560ms	5	5	100.00
		hmac_test_sha384_vectors	38.916m	212.729ms	5	5	100.00
		hmac_test_sha512_vectors	37.320m	2.000s	5	5	100.00
		hmac_test_hmac256_vectors	1.176m	7.163ms	5	5	100.00
		hmac_test_hmac384_vectors	1.584m	19.391ms	5	5	100.00
		hmac_test_hmac512_vectors	1.898m	83.439ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.950s	680.637us	50	50	100.00
		hmac_long_msg	3.031m	96.531ms	50	50	100.00
		hmac_back_pressure	1.326m	1.584ms	50	50	100.00
		hmac_datapath_stress	22.337m	16.413ms	50	50	100.00
		hmac_burst_wr	57.210s	6.165ms	50	50	100.00
		hmac_error	4.240m	124.148ms	50	50	100.00
		hmac_wipe_secret	2.238m	36.220ms	50	50	100.00
		hmac_test_sha256_vectors	9.830m	54.560ms	5	5	100.00
		hmac_test_sha384_vectors	38.916m	212.729ms	5	5	100.00
		hmac_test_sha512_vectors	37.320m	2.000s	5	5	100.00
		hmac_test_hmac256_vectors	1.176m	7.163ms	5	5	100.00
		hmac_test_hmac384_vectors	1.584m	19.391ms	5	5	100.00
		hmac_test_hmac512_vectors	1.898m	83.439ms	5	5	100.00
		hmac_stress_all	56.221m	153.683ms	48	50	96.00
V2	stress_all	hmac_stress_all	56.221m	153.683ms	48	50	96.00
V2	alert_test	hmac_alert_test	0.580s	31.346us	50	50	100.00
V2	intr_test	hmac_intr_test	0.580s	13.578us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.140s	958.407us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.140s	958.407us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.720s	24.198us	5	5	100.00
		hmac_csr_rw	0.880s	30.348us	20	20	100.00
		hmac_csr_aliasing	7.000s	1.743ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	689.217us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.720s	24.198us	5	5	100.00
		hmac_csr_rw	0.880s	30.348us	20	20	100.00
		hmac_csr_aliasing	7.000s	1.743ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	689.217us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	0.960s	102.348us	5	5	100.00
		hmac_tl_intg_err	3.890s	723.063us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.890s	723.063us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.950s	680.637us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	4.274m	15.734ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			653	660	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 1.hmac_stress_all_with_rand_reset.47076125048746829721999789243822033507882583519021791180852489855807971286650
      Line 6929, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3270270064 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3270270064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.hmac_stress_all_with_rand_reset.33803485930960497115969953654251396825846074983838637674423097188093521094687
      Line 15914, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10584831278 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 10584831278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 4.hmac_stress_all_with_rand_reset.105803772707065432407628796815775282818631836038876428050766614780597121193635
      Line 17473, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7874354086 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 7874354086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.hmac_stress_all_with_rand_reset.79223233113901740422680929700679579446619550599703742679155232907814997424165
      Line 3085, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2163990523 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2163990523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:

  • Test hmac_stress_all has 2 failures.

    • 6.hmac_stress_all.27217218540553942752854221451739753886773971432199256894872484188311159212368
      Line 438, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_stress_all/latest/run.log

        UVM_ERROR @ 1445192462 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 1445192462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.hmac_stress_all.26513706950215568091847123078054211129642706523415571882135802870410415663801
      Line 444, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_stress_all/latest/run.log

        UVM_ERROR @ 624188100 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 624188100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 5.hmac_stress_all_with_rand_reset.84789153209170026532873288598580414638040668404050088817750175837353392900182
      Line 8189, in log /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3396867174 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3396867174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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