HMAC Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	25.020s	5.466ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.450s	36.442us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.360s	29.191us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	23.860s	26.243ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.870s	157.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	48.146m	1.155s	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.360s	29.191us	20	20	100.00
		hmac_csr_aliasing	10.870s	157.363us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.886m	16.690ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.671m	1.778ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	15.713m	176.277ms	5	5	100.00
		hmac_test_sha384_vectors	55.087m	279.922ms	4	5	80.00
		hmac_test_sha512_vectors	57.058m	186.801ms	5	5	100.00
		hmac_test_hmac256_vectors	1.819m	7.471ms	5	5	100.00
		hmac_test_hmac384_vectors	1.985m	23.706ms	5	5	100.00
		hmac_test_hmac512_vectors	1.872m	9.406ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.704m	21.946ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	32.019m	13.437ms	50	50	100.00
V2	error	hmac_error	5.748m	20.069ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.343m	7.959ms	50	50	100.00
V2	save_and_restore	hmac_smoke	25.020s	5.466ms	50	50	100.00
		hmac_long_msg	4.886m	16.690ms	50	50	100.00
		hmac_back_pressure	2.671m	1.778ms	50	50	100.00
		hmac_datapath_stress	32.019m	13.437ms	50	50	100.00
		hmac_burst_wr	1.704m	21.946ms	50	50	100.00
		hmac_stress_all	2.054h	507.764ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	25.020s	5.466ms	50	50	100.00
		hmac_long_msg	4.886m	16.690ms	50	50	100.00
		hmac_back_pressure	2.671m	1.778ms	50	50	100.00
		hmac_datapath_stress	32.019m	13.437ms	50	50	100.00
		hmac_wipe_secret	3.343m	7.959ms	50	50	100.00
		hmac_test_sha256_vectors	15.713m	176.277ms	5	5	100.00
		hmac_test_sha384_vectors	55.087m	279.922ms	4	5	80.00
		hmac_test_sha512_vectors	57.058m	186.801ms	5	5	100.00
		hmac_test_hmac256_vectors	1.819m	7.471ms	5	5	100.00
		hmac_test_hmac384_vectors	1.985m	23.706ms	5	5	100.00
		hmac_test_hmac512_vectors	1.872m	9.406ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	25.020s	5.466ms	50	50	100.00
		hmac_long_msg	4.886m	16.690ms	50	50	100.00
		hmac_back_pressure	2.671m	1.778ms	50	50	100.00
		hmac_datapath_stress	32.019m	13.437ms	50	50	100.00
		hmac_burst_wr	1.704m	21.946ms	50	50	100.00
		hmac_error	5.748m	20.069ms	50	50	100.00
		hmac_wipe_secret	3.343m	7.959ms	50	50	100.00
		hmac_test_sha256_vectors	15.713m	176.277ms	5	5	100.00
		hmac_test_sha384_vectors	55.087m	279.922ms	4	5	80.00
		hmac_test_sha512_vectors	57.058m	186.801ms	5	5	100.00
		hmac_test_hmac256_vectors	1.819m	7.471ms	5	5	100.00
		hmac_test_hmac384_vectors	1.985m	23.706ms	5	5	100.00
		hmac_test_hmac512_vectors	1.872m	9.406ms	5	5	100.00
		hmac_stress_all	2.054h	507.764ms	50	50	100.00
V2	stress_all	hmac_stress_all	2.054h	507.764ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.960s	14.297us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	48.726us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	6.410s	926.705us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	6.410s	926.705us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.450s	36.442us	5	5	100.00
		hmac_csr_rw	1.360s	29.191us	20	20	100.00
		hmac_csr_aliasing	10.870s	157.363us	5	5	100.00
		hmac_same_csr_outstanding	3.600s	162.649us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.450s	36.442us	5	5	100.00
		hmac_csr_rw	1.360s	29.191us	20	20	100.00
		hmac_csr_aliasing	10.870s	157.363us	5	5	100.00
		hmac_same_csr_outstanding	3.600s	162.649us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.600s	1.089ms	5	5	100.00
		hmac_tl_intg_err	6.420s	920.369us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.420s	920.369us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	25.020s	5.466ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.783m	29.715ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			656	660	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	95.26	97.27	100.00	97.06	98.12	97.97	99.85

Failure Buckets

Job timed out after * minutes has 1 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 0.hmac_test_sha384_vectors.62469627195438127939783159368367090251778839390883462659683475674312341615456
    Log /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 7.hmac_stress_all_with_rand_reset.109656920237897646672545847098670153905612912897928677271884949383825490417320
    Line 13197, in log /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12647845748 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 12647845748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 8.hmac_stress_all_with_rand_reset.94089666035053929440996879680891988493903484168799678580345169732634684335960
    Line 17526, in log /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5992630925 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5992630925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 9.hmac_stress_all_with_rand_reset.44208554411297752742031483312472409239596522494494030986483059644233768991347
    Line 75, in log /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  58978043 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  58978043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e733a8ef8a`