HMAC Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	21.510s	1.075ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.410s	84.309us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.390s	19.628us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.730s	1.332ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	12.240s	1.631ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.348m	218.066ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.390s	19.628us	20	20	100.00
		hmac_csr_aliasing	12.240s	1.631ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.314m	16.352ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.299m	10.190ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.688m	219.775ms	5	5	100.00
		hmac_test_sha384_vectors	46.523m	2.828s	5	5	100.00
		hmac_test_sha512_vectors	46.307m	402.665ms	5	5	100.00
		hmac_test_hmac256_vectors	1.752m	21.740ms	5	5	100.00
		hmac_test_hmac384_vectors	1.970m	18.682ms	5	5	100.00
		hmac_test_hmac512_vectors	2.480m	83.688ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.712m	15.764ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	30.438m	35.876ms	50	50	100.00
V2	error	hmac_error	4.338m	26.798ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.825m	13.412ms	50	50	100.00
V2	save_and_restore	hmac_smoke	21.510s	1.075ms	50	50	100.00
		hmac_long_msg	4.314m	16.352ms	50	50	100.00
		hmac_back_pressure	2.299m	10.190ms	50	50	100.00
		hmac_datapath_stress	30.438m	35.876ms	50	50	100.00
		hmac_burst_wr	1.712m	15.764ms	49	50	98.00
		hmac_stress_all	1.686h	42.366ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	21.510s	1.075ms	50	50	100.00
		hmac_long_msg	4.314m	16.352ms	50	50	100.00
		hmac_back_pressure	2.299m	10.190ms	50	50	100.00
		hmac_datapath_stress	30.438m	35.876ms	50	50	100.00
		hmac_wipe_secret	2.825m	13.412ms	50	50	100.00
		hmac_test_sha256_vectors	11.688m	219.775ms	5	5	100.00
		hmac_test_sha384_vectors	46.523m	2.828s	5	5	100.00
		hmac_test_sha512_vectors	46.307m	402.665ms	5	5	100.00
		hmac_test_hmac256_vectors	1.752m	21.740ms	5	5	100.00
		hmac_test_hmac384_vectors	1.970m	18.682ms	5	5	100.00
		hmac_test_hmac512_vectors	2.480m	83.688ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	21.510s	1.075ms	50	50	100.00
		hmac_long_msg	4.314m	16.352ms	50	50	100.00
		hmac_back_pressure	2.299m	10.190ms	50	50	100.00
		hmac_datapath_stress	30.438m	35.876ms	50	50	100.00
		hmac_burst_wr	1.712m	15.764ms	49	50	98.00
		hmac_error	4.338m	26.798ms	50	50	100.00
		hmac_wipe_secret	2.825m	13.412ms	50	50	100.00
		hmac_test_sha256_vectors	11.688m	219.775ms	5	5	100.00
		hmac_test_sha384_vectors	46.523m	2.828s	5	5	100.00
		hmac_test_sha512_vectors	46.307m	402.665ms	5	5	100.00
		hmac_test_hmac256_vectors	1.752m	21.740ms	5	5	100.00
		hmac_test_hmac384_vectors	1.970m	18.682ms	5	5	100.00
		hmac_test_hmac512_vectors	2.480m	83.688ms	5	5	100.00
		hmac_stress_all	1.686h	42.366ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.686h	42.366ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.920s	28.260us	50	50	100.00
V2	intr_test	hmac_intr_test	1.030s	17.783us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.920s	1.039ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.920s	1.039ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.410s	84.309us	5	5	100.00
		hmac_csr_rw	1.390s	19.628us	20	20	100.00
		hmac_csr_aliasing	12.240s	1.631ms	5	5	100.00
		hmac_same_csr_outstanding	3.880s	474.415us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.410s	84.309us	5	5	100.00
		hmac_csr_rw	1.390s	19.628us	20	20	100.00
		hmac_csr_aliasing	12.240s	1.631ms	5	5	100.00
		hmac_same_csr_outstanding	3.880s	474.415us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.730s	511.095us	5	5	100.00
		hmac_tl_intg_err	6.840s	295.215us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.840s	295.215us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	21.510s	1.075ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.780m	13.165ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:
- Test hmac_burst_wr has 1 failures.
  - 13.hmac_burst_wr.62468472497568278971255472918064049872134959642321753214362338654033029266178
    Line 1198, in log /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 1024729719 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 1024729719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_stress_all has 1 failures.
  - 36.hmac_stress_all.75837580517031312073956092350449512209293382991579580287858559309170861191196
    Line 49848, in log /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 4320634245 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 4320634245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 7.hmac_stress_all_with_rand_reset.105368016051866283223872124511725512333528355884186465900326564894406435999057
    Line 3331, in log /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1558707083 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1558707083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`