HMAC Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	19.900s	8.373ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.440s	70.061us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.480s	31.708us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	19.220s	3.412ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.690s	1.854ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.021m	236.702ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.480s	31.708us	20	20	100.00
		hmac_csr_aliasing	10.690s	1.854ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.201m	16.287ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.110m	6.108ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	13.782m	54.498ms	5	5	100.00
		hmac_test_sha384_vectors	46.401m	1.899s	5	5	100.00
		hmac_test_sha512_vectors	50.395m	428.155ms	5	5	100.00
		hmac_test_hmac256_vectors	1.380m	8.690ms	5	5	100.00
		hmac_test_hmac384_vectors	2.294m	13.642ms	5	5	100.00
		hmac_test_hmac512_vectors	2.913m	25.186ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	2.139m	15.703ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	26.548m	97.125ms	50	50	100.00
V2	error	hmac_error	5.131m	8.357ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.158m	49.145ms	50	50	100.00
V2	save_and_restore	hmac_smoke	19.900s	8.373ms	50	50	100.00
		hmac_long_msg	4.201m	16.287ms	50	50	100.00
		hmac_back_pressure	2.110m	6.108ms	50	50	100.00
		hmac_datapath_stress	26.548m	97.125ms	50	50	100.00
		hmac_burst_wr	2.139m	15.703ms	49	50	98.00
		hmac_stress_all	1.585h	739.683ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	19.900s	8.373ms	50	50	100.00
		hmac_long_msg	4.201m	16.287ms	50	50	100.00
		hmac_back_pressure	2.110m	6.108ms	50	50	100.00
		hmac_datapath_stress	26.548m	97.125ms	50	50	100.00
		hmac_wipe_secret	3.158m	49.145ms	50	50	100.00
		hmac_test_sha256_vectors	13.782m	54.498ms	5	5	100.00
		hmac_test_sha384_vectors	46.401m	1.899s	5	5	100.00
		hmac_test_sha512_vectors	50.395m	428.155ms	5	5	100.00
		hmac_test_hmac256_vectors	1.380m	8.690ms	5	5	100.00
		hmac_test_hmac384_vectors	2.294m	13.642ms	5	5	100.00
		hmac_test_hmac512_vectors	2.913m	25.186ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	19.900s	8.373ms	50	50	100.00
		hmac_long_msg	4.201m	16.287ms	50	50	100.00
		hmac_back_pressure	2.110m	6.108ms	50	50	100.00
		hmac_datapath_stress	26.548m	97.125ms	50	50	100.00
		hmac_burst_wr	2.139m	15.703ms	49	50	98.00
		hmac_error	5.131m	8.357ms	50	50	100.00
		hmac_wipe_secret	3.158m	49.145ms	50	50	100.00
		hmac_test_sha256_vectors	13.782m	54.498ms	5	5	100.00
		hmac_test_sha384_vectors	46.401m	1.899s	5	5	100.00
		hmac_test_sha512_vectors	50.395m	428.155ms	5	5	100.00
		hmac_test_hmac256_vectors	1.380m	8.690ms	5	5	100.00
		hmac_test_hmac384_vectors	2.294m	13.642ms	5	5	100.00
		hmac_test_hmac512_vectors	2.913m	25.186ms	5	5	100.00
		hmac_stress_all	1.585h	739.683ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.585h	739.683ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.940s	15.829us	50	50	100.00
V2	intr_test	hmac_intr_test	0.990s	18.887us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.680s	224.481us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.680s	224.481us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.440s	70.061us	5	5	100.00
		hmac_csr_rw	1.480s	31.708us	20	20	100.00
		hmac_csr_aliasing	10.690s	1.854ms	5	5	100.00
		hmac_same_csr_outstanding	3.620s	156.516us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.440s	70.061us	5	5	100.00
		hmac_csr_rw	1.480s	31.708us	20	20	100.00
		hmac_csr_aliasing	10.690s	1.854ms	5	5	100.00
		hmac_same_csr_outstanding	3.620s	156.516us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.600s	90.707us	5	5	100.00
		hmac_tl_intg_err	6.460s	448.963us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.460s	448.963us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	19.900s	8.373ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	13.361m	61.563ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			654	660	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.40	97.22	100.00	94.12	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 2.hmac_stress_all_with_rand_reset.51902739260713946247625594136712864154672826999827094928037145756157479267621
      Line 2434, in log /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1730424181 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1730424181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.hmac_stress_all_with_rand_reset.64592695326836293887040834357793199056382009332694044420087829623985662496020
      Line 52510, in log /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5002847712 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 5002847712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 1.hmac_stress_all_with_rand_reset.63698615317078904208105378903627850316743451406777999759986446875822251549516
      Line 4704, in log /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2209095638 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2209095638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 4.hmac_stress_all_with_rand_reset.41269239088951434858801027916630577960815122275188226917045955498732066174884
      Line 9211, in log /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3202339378 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3202339378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 7.hmac_stress_all_with_rand_reset.46049010640321387546527802305572500325709186478146778773240190864437705682966
      Line 14935, in log /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20253016087 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 20253016087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_burst_wr has 1 failures.

    • 36.hmac_burst_wr.16420151622698268545542748022883672345858906080845937605345507181589948129330
      Line 367, in log /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 459297991 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 459297991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.08.28_06.55.20
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