042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.946m | 2.963ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.570s | 1.727ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.710s | 21.791us | 4 | 5 | 80.00 |
| V1 | csr_rw | i2c_csr_rw | 0.720s | 61.482us | 16 | 20 | 80.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 2.240s | 156.095us | 2 | 5 | 40.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.290s | 257.427us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.340s | 51.850us | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.720s | 61.482us | 16 | 20 | 80.00 |
| i2c_csr_aliasing | 1.290s | 257.427us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 145 | 155 | 93.55 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.990s | 95.606us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 56.122m | 64.840ms | 34 | 50 | 68.00 |
| V2 | host_perf | i2c_host_perf | 39.612m | 77.300ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.700s | 21.859us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 13.211m | 15.032ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 17.921m | 6.721ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.140s | 165.592us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.360s | 6.488ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.100s | 426.098us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.266m | 4.937ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 53.390s | 7.140ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 4.648m | 7.433ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 4.585m | 5.833ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 10.700s | 10.027ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.820s | 1.101ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 58.591m | 87.413ms | 43 | 50 | 86.00 |
| V2 | target_perf | i2c_target_perf | 5.850s | 19.681ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 5.633m | 15.195ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.831m | 5.344ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.460s | 2.353ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.260m | 10.079ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.777m | 10.038ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 58.363m | 48.936ms | 45 | 50 | 90.00 |
| i2c_target_stress_rd | 1.831m | 5.344ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 55.675m | 48.255ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.960s | 12.287ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 35.506m | 25.383ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.120s | 1.517ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.340s | 3.145ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.630s | 42.088us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.710s | 108.970us | 42 | 50 | 84.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.260s | 227.538us | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.260s | 227.538us | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.710s | 21.791us | 4 | 5 | 80.00 |
| i2c_csr_rw | 0.720s | 61.482us | 16 | 20 | 80.00 | ||
| i2c_csr_aliasing | 1.290s | 257.427us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.980s | 46.266us | 15 | 20 | 75.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.710s | 21.791us | 4 | 5 | 80.00 |
| i2c_csr_rw | 0.720s | 61.482us | 16 | 20 | 80.00 | ||
| i2c_csr_aliasing | 1.290s | 257.427us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.980s | 46.266us | 15 | 20 | 75.00 | ||
| V2 | TOTAL | 1445 | 1492 | 96.85 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.810s | 235.425us | 17 | 20 | 85.00 |
| i2c_sec_cm | 0.940s | 61.983us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.810s | 235.425us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 12.997m | 11.833ms | 4 | 50 | 8.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.335m | 19.192ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 4 | 100 | 4.00 | |||
| TOTAL | 1616 | 1772 | 91.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 3 | 42.86 |
| V2 | 32 | 32 | 25 | 78.12 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.62 | 99.17 | 96.66 | 100.00 | 96.52 | 98.24 | 100.00 | 92.75 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 85 failures:
0.i2c_host_stress_all.14789391813773692927239281338327624567086377687051862163938310046058372799491
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:b6f3130b-b39c-4c9c-bfd4-d1d103db4264
14.i2c_host_stress_all.89533255884670240604937959203762897559569279153611154319727836813400144849124
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
Job ID: smart:0342f46f-070b-4dc6-a5aa-80c78a117d4d
... and 14 more failures.
0.i2c_host_stress_all_with_rand_reset.23179245727313912496475781084673983737689573413806165320359867519005108537006
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9825ddda-2fe7-4b4e-ab92-e4fc66810973
1.i2c_host_stress_all_with_rand_reset.12713335090808827307471416671963360106281626859685573651612004422237858357070
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b8627a8e-3e08-4a67-89df-f72b62639ba7
... and 44 more failures.
4.i2c_target_stress_all_with_rand_reset.53630515878765949065432861203361584878444548065653420921092132478820762923266
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e5ed4d9b-71f7-4dac-86ce-be7d529917bd
18.i2c_target_stress_all_with_rand_reset.73705167597218456851355025474654773520763439700741523560185074638002078815764
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d3c12d0a-ff2d-44c8-a242-3f8868608dfb
... and 4 more failures.
11.i2c_target_stress_all.56697298435260102260318925980573836405198619262483978098149173255856478931278
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
Job ID: smart:8cac1257-7efe-4b7e-8ddf-f826710791a4
18.i2c_target_stress_all.63014591950661466126675255639209079531165665006106542063978827978235845659039
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
Job ID: smart:08f7c0c2-45c4-44c3-b70d-dd5f677743e7
... and 5 more failures.
17.i2c_target_stretch.113475847882647923332822301352419174963886612774654318482774559017715173685075
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
Job ID: smart:7fd40f4d-7dc3-41f8-9d20-e4b14959b822
21.i2c_target_stretch.97160664596993884082562148888861187604411179302755057574945681690149774338024
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
Job ID: smart:09075042-de59-4fa9-bf3a-dd3f2597a165
... and 3 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 25 failures:
Test i2c_intr_test has 8 failures.
0.i2c_intr_test.32632676036996359298178632042204851597036896577662629871550739988376356545697
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_intr_test/latest/run.log
[make]: simulate
cd /workspace/0.i2c_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470681249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3470681249
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
20.i2c_intr_test.91713850226680466737234616048691336687931752765840739197476566246988581904003
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_intr_test/latest/run.log
[make]: simulate
cd /workspace/20.i2c_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745114243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2745114243
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
Test i2c_csr_bit_bash has 3 failures.
0.i2c_csr_bit_bash.52074409030536423175818293861855807823142463262957802476548862168611595201605
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.i2c_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875539525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.875539525
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.i2c_csr_bit_bash.97486615032298939011553625763521469937037725301832345235102865124223801756137
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/1.i2c_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637667817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.637667817
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test i2c_csr_mem_rw_with_rand_reset has 2 failures.
0.i2c_csr_mem_rw_with_rand_reset.39103328742928167272000888226958247502249513677817285854749848982126774101310
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432003902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1432003902
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.i2c_csr_mem_rw_with_rand_reset.80579050632799444384337722037068806660086358797735936370078528680043868733239
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858041143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2858041143
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test i2c_csr_rw has 4 failures.
3.i2c_csr_rw.43130240525171695254361193510147007153828064918702537923892258073993504048533
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_rw/latest/run.log
[make]: simulate
cd /workspace/3.i2c_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491289493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1491289493
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
5.i2c_csr_rw.6870175111065058943003674445303758460862791963903639663764549081920598301219
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_csr_rw/latest/run.log
[make]: simulate
cd /workspace/5.i2c_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329898531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.329898531
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:51 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more failures.
Test i2c_csr_hw_reset has 1 failures.
4.i2c_csr_hw_reset.43425873317424206681823200417725413035150286801881981092990390855913368785066
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/4.i2c_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589083306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3589083306
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more tests.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 12 failures:
6.i2c_target_stress_all_with_rand_reset.12789977775113273449737144550307181937603260411777514370626346720484736202015
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8316190795 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 9 [0x9])
UVM_INFO @ 8316190795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.113091927967606886785005611062541124886281382164879034862521079874893607446340
Line 339, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18460511095 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 18 [0x12])
UVM_INFO @ 18460511095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 8 failures:
0.i2c_target_stress_all_with_rand_reset.64633935061128635606718905338402291659015099708295326136571689485014199203146
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1409459712 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x2bb0d714) == 0x0
UVM_INFO @ 1409459712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.83839396962317594756895365598306322591282785559544625138046224246532139257130
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11014610570 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf0938d14) == 0x0
UVM_INFO @ 11014610570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 8 failures:
1.i2c_target_stress_all_with_rand_reset.85048140999128180573167054678974483768593581981328163463117221230578244652955
Line 324, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5150105256 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5150105256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.75000164774361891989755956790392708644762829461273569872461145631521243203214
Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5561823871 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5561823871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Offending 'scl_i' has 7 failures:
Test i2c_same_csr_outstanding has 1 failures.
1.i2c_same_csr_outstanding.5298580869702516385155038425823906287702765085046904166372793907625410567635
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 16209587 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 16209587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 6 failures.
5.i2c_target_stress_all_with_rand_reset.38866126500788174221523755919000161562291021009267847358470604954575660022582
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 2490812698 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 2490812698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all_with_rand_reset.82909268202849630867758869080295569508130850552125944178952498133979821297107
Line 344, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 5690034208 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 5690034208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 5 failures:
7.i2c_target_stress_all_with_rand_reset.105148488161656358772219539245223037149665640530546818700673487707307352373100
Line 319, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36059113781 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 36059113781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.28653446606992728273891154284553123728158129163666169304394000993532645590630
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 567087257 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 567087257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
31.i2c_target_stress_all_with_rand_reset.49917859154453147487235432739889619368988717724291940492100499094405823291961
Line 338, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7933186323 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (155 [0x9b] vs 79 [0x4f])
UVM_INFO @ 7933186323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.i2c_target_stress_all_with_rand_reset.33694415820543786542618539612959991348657311479344026718759011296432013537748
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3617289099 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (157 [0x9d] vs 147 [0x93])
UVM_INFO @ 3617289099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_o' has 1 failures:
8.i2c_same_csr_outstanding.28040759500105512180782546904800862537822017717302226656257868760328293464019
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 9179193 ps: (i2c_fsm.sv:1357) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 9179193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 1 failures:
10.i2c_target_stress_all_with_rand_reset.1556257767438973355622279078488041924921103549420003804903524970539639939940
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4296605258 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4296605258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:78) [target_smoke_vseq] wait timeout occurred! has 1 failures:
33.i2c_target_stress_all_with_rand_reset.72268269950396111278943162343814898498811122230214330052209327352018694306283
Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 35111972687 ps: (i2c_target_smoke_vseq.sv:78) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 35111972687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:791) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
40.i2c_target_stress_all_with_rand_reset.7882955365165196228204220014479987916554984088155794581422154682191303930331
Line 425, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19191518585 ps: (i2c_scoreboard.sv:791) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (0 [0x0] vs 209 [0xd1])
UVM_INFO @ 19191518585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---