4d88b9516c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 3.266m | 11.491ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 48.710s | 6.776ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 28.474us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.760s | 18.819us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.060s | 295.890us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.360s | 67.034us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.630s | 59.535us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.760s | 18.819us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.360s | 67.034us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.120s | 47.170us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.178m | 21.039ms | 34 | 50 | 68.00 |
| V2 | host_perf | i2c_host_perf | 29.113m | 72.263ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.720s | 18.378us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 15.072m | 13.205ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 17.231m | 9.770ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.150s | 161.140us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 53.440s | 983.930us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.500s | 295.612us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.620m | 3.572ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 54.280s | 1.257ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 5.869m | 12.818ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 3.609m | 2.512ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 10.860s | 2.123ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.770s | 10.330ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 43.052m | 70.105ms | 37 | 50 | 74.00 |
| V2 | target_perf | i2c_target_perf | 6.290s | 4.457ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 3.794m | 15.070ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.072m | 1.549ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.650s | 2.201ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.732m | 10.032ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.231m | 10.089ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 59.679m | 49.624ms | 42 | 50 | 84.00 |
| i2c_target_stress_rd | 1.072m | 1.549ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 26.669m | 71.391ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.800s | 2.120ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 55.910m | 19.610ms | 39 | 50 | 78.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.830s | 2.924ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.610s | 730.164us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.680s | 26.038us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 33.632us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.670s | 253.274us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.670s | 253.274us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 28.474us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.760s | 18.819us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.360s | 67.034us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.050s | 66.942us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 28.474us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.760s | 18.819us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.360s | 67.034us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.050s | 66.942us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1442 | 1492 | 96.65 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.970s | 458.638us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.010s | 64.162us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.970s | 458.638us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 10.497m | 19.078ms | 2 | 50 | 4.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.694m | 34.039ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 2 | 100 | 2.00 | |||
| TOTAL | 1624 | 1772 | 91.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 32 | 32 | 26 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.60 | 99.27 | 96.93 | 100.00 | 95.65 | 98.57 | 100.00 | 92.75 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 101 failures:
0.i2c_host_stress_all_with_rand_reset.75047668117233520402494698380165521325320974979447535917400516294672961542497
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2a6de205-68ea-4ece-a1f7-f77eb4292bd3
1.i2c_host_stress_all_with_rand_reset.46179536487660481177676371141751171066096892372216414678186359565011967714164
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:981c2c4a-447f-487c-9bc8-3d69cb8d6ca1
... and 45 more failures.
1.i2c_target_stretch.57582297247487118247439953235590014884661038652572104282200528894940226641665
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
Job ID: smart:4e95b627-f026-4cad-b28c-3aa37337cbe0
2.i2c_target_stretch.82200472256858365950346669437425163185402290814636607054439237653670978411550
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:c5fc6621-f84f-4e46-942e-7e455a051b03
... and 9 more failures.
3.i2c_host_stress_all.101906404405906860532893137259439838484417306139658108630374013701411519524293
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job ID: smart:d4e75d69-cab6-4b5f-8c05-a5ad645bb604
5.i2c_host_stress_all.733814168186530394233697926397671772655535601953180305266312702147893328626
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:2ebba498-0ec2-42f3-b7d7-76cf7e2c38ef
... and 14 more failures.
3.i2c_target_stress_all.83948852458789392601856974277222803113784313497344089770492833113982014713633
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
Job ID: smart:786588b7-7b41-4936-8692-2f0f96a6389e
12.i2c_target_stress_all.92654025351366966291246484957248233194298433893859004534198382946207002985455
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
Job ID: smart:8ba6b36b-756c-4128-b5cf-a7af4cee1b66
... and 11 more failures.
10.i2c_target_stress_wr.79823247916872495165077094176535752853019067091334351441444030689778369557484
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_wr/latest/run.log
Job ID: smart:922a647c-38f6-4494-979a-a6640b1abbdc
18.i2c_target_stress_wr.106350632298467712830309160228886699965918227735835365622981575103091948791945
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_wr/latest/run.log
Job ID: smart:ab8211f8-eeb9-417e-a2db-bf542d2a8c5b
... and 6 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 18 failures:
3.i2c_target_stress_all_with_rand_reset.97152451376474988247371405432380954047132330091849255395727289898777962437523
Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 499648337 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 499648337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.14181289920735826079917922720335013011895666928316526941196300457055357199667
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 162345566 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 162345566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 13 failures:
0.i2c_target_stress_all_with_rand_reset.54478950345594581793366400147366767531510633205949392919997429203667331303822
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4600073698 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8811ff94) == 0x0
UVM_INFO @ 4600073698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.43970393891093519147885610914307997163984942460949870759381996326054895952567
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2042291441 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xed4c5514) == 0x0
UVM_INFO @ 2042291441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 9 failures:
23.i2c_target_stress_all_with_rand_reset.109050845382401130585315308819896751529724993649901998676315486204115365665412
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9723927937 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 8 [0x8])
UVM_INFO @ 9723927937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_stress_all_with_rand_reset.9673000047726820825996258418835806760845828107352073651853432722276876797676
Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5431162600 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 1 [0x1])
UVM_INFO @ 5431162600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 2 failures:
9.i2c_target_stress_all_with_rand_reset.16777990957156121800825568075351133340956609926418348637753078996316891807526
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13174570546 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 13174570546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_stress_all_with_rand_reset.78411521390916842622465450146172969344963378257443513817205946098570703908773
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1057452907 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 1057452907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
31.i2c_target_stress_all_with_rand_reset.23677834634503604330985238076977292838818579923223262553476097290003566979610
Line 337, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5531289289 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (205 [0xcd] vs 204 [0xcc])
UVM_INFO @ 5531289289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.i2c_target_stress_all_with_rand_reset.76421097885764706487710879240035458223198712519135670449130912532650085993090
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 124900101 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (114 [0x72] vs 74 [0x4a])
UVM_INFO @ 124900101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))' has 1 failures:
1.i2c_same_csr_outstanding.89393917577024997117757661484141798498194277543655668792611629422893223877713
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))'
UVM_ERROR @ 38671537 ps: (i2c_fsm.sv:1366) [ASSERT FAILED] SclSdaChangeNotSimultaneous_A
UVM_INFO @ 38671537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 1 failures:
36.i2c_target_stress_all_with_rand_reset.108608067336132150538187015554304057452578791604338858369203477496553810283286
Line 355, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 26377406137 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 26377406137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:56) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
39.i2c_host_stress_all_with_rand_reset.18788601207509533181129072702324054504516890060306413779644464163318777977298
Line 3495, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 53626706054 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 53626706054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---