796f9fb805| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 3.389m | 10.044ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.007m | 12.834ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 23.723us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.810s | 24.636us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.440s | 420.255us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.370s | 108.549us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.490s | 481.654us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.810s | 24.636us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.370s | 108.549us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.190s | 167.169us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 56.142m | 86.413ms | 31 | 50 | 62.00 |
| V2 | host_perf | i2c_host_perf | 43.772m | 53.085ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 100.515us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 14.466m | 13.346ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 18.329m | 26.992ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.210s | 268.554us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 36.430s | 2.017ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.840s | 271.833us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 6.196m | 3.827ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.520s | 1.976ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 8.104m | 3.449ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.187m | 5.965ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.240s | 6.493ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.680s | 4.202ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 53.659m | 39.838ms | 42 | 50 | 84.00 |
| V2 | target_perf | i2c_target_perf | 6.350s | 8.003ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 6.383m | 16.823ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.358m | 1.987ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.810s | 9.257ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.342m | 10.094ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.775m | 10.088ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 47.843m | 45.685ms | 43 | 50 | 86.00 |
| i2c_target_stress_rd | 1.358m | 1.987ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 31.731m | 64.671ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.820s | 2.260ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 59.164m | 34.949ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.520s | 7.880ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.950s | 967.815us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.670s | 15.124us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 182.693us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.760s | 462.565us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.760s | 462.565us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 23.723us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 24.636us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.370s | 108.549us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.130s | 181.945us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 23.723us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 24.636us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.370s | 108.549us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.130s | 181.945us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1450 | 1492 | 97.18 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.090s | 428.792us | 19 | 20 | 95.00 |
| i2c_sec_cm | 1.010s | 64.890us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.090s | 428.792us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.682m | 50.286ms | 3 | 50 | 6.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.948m | 8.800ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 3 | 100 | 3.00 | |||
| TOTAL | 1632 | 1772 | 92.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 32 | 32 | 26 | 81.25 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.63 | 99.27 | 96.92 | 100.00 | 95.65 | 98.57 | 100.00 | 92.96 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 94 failures:
0.i2c_host_stress_all.30702416593069473536972733755546502872006428339644292547633747202153745636290
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:b07d014d-0c0e-4eeb-b056-7cbc0c97756d
1.i2c_host_stress_all.15945477759776809933107198130874522913729076766737387411827239520190308881891
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:b8471987-8575-47e5-a212-f6d24d030ad8
... and 17 more failures.
0.i2c_host_stress_all_with_rand_reset.40069485616877123514237712211681450353598770572367345658708945183392130451025
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:30d8f1a7-191c-4f5b-9a7d-b5573208181d
1.i2c_host_stress_all_with_rand_reset.12382423664199106757948707644978099715325981425271698849991505801726659410812
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:dfe596f9-cb87-40c9-9406-03065aff708f
... and 45 more failures.
2.i2c_target_stretch.44829173113980979028990558563483129308823868817013175002449973016124312154233
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:1b09bbcc-cee3-4fd7-b6af-121c20c0cfe1
7.i2c_target_stretch.58042035082136048874458472426272466662282018657882462313421700819922592728187
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
Job ID: smart:a70f061d-5a8d-4f4a-91be-e691fb1207dc
... and 4 more failures.
4.i2c_target_stress_wr.95302594071599889729830281029556898130340120000896576646253602777300076250227
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_wr/latest/run.log
Job ID: smart:4e42deb7-cf86-4c22-ad25-c893731e1e4f
17.i2c_target_stress_wr.94951523829073981761407224031061016346182480844720771756100626177066507433996
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_wr/latest/run.log
Job ID: smart:c9000ddb-cedf-4387-82ea-fed314adebc0
... and 5 more failures.
5.i2c_target_stress_all_with_rand_reset.6913867903016764798370428216905974852600052587561868319609250166935248739510
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:79ee2028-4095-4a55-908f-6ba5f0778900
16.i2c_target_stress_all_with_rand_reset.29859548843328086327606285477311760128865059998559295568929434748313562025364
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:1ad386b1-aa5c-4720-8e02-6c30967bea58
... and 5 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 12 failures:
1.i2c_target_stress_all_with_rand_reset.85949389635790776917599799566929967368706101721567706427287183005072224941952
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 183296724 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 183296724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.30357124028572544460917241428405639857083773981672474767632845113658973105419
Line 324, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17335154222 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 17335154222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 12 failures:
3.i2c_target_stress_all_with_rand_reset.7685896504230075460472783217148826189909734363997659531657555474258798174492
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2986613997 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 4 [0x4])
UVM_INFO @ 2986613997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all_with_rand_reset.103880019223877019406814957693948502471187607077714868920673146889582530107690
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4664015358 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 8 [0x8])
UVM_INFO @ 4664015358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 8 failures:
0.i2c_target_stress_all_with_rand_reset.12876012308868567855095098407549801734073508145252167718778591501959525236871
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 7711296574 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x4341bc94) == 0x0
UVM_INFO @ 7711296574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.71838188575408905690162720698252979227840382312489892554190727895134252174333
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1585607630 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xa0e21694) == 0x0
UVM_INFO @ 1585607630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Offending 'scl_i' has 6 failures:
7.i2c_target_stress_all_with_rand_reset.19284416378204308337090967656882350243254047899828794925394542167202493743052
Line 351, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 30380600877 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 30380600877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_stress_all_with_rand_reset.52646133139117336349724139576270760718913098776392024671372436154875169074884
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 4210110014 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 4210110014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
8.i2c_same_csr_outstanding.80433224733270210500788452728860855687300382490005521587330424565450525217149
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 4183093 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 4183093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 4 failures:
6.i2c_target_stress_all_with_rand_reset.58658697383034411886273705072054656983009746601738964929730675857507809214981
Line 335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10071397765 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 10071397765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.109546767058981963953167276590396229015252062458830821059948315544665510091111
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16342899 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 16342899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
9.i2c_target_stress_all.54301848808863665700436178188013751354701415488123620104244387394436625034880
Line 317, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))' has 1 failures:
17.i2c_tl_intg_err.36771553198987398503539611338602172712747717494638488445617731408434502614908
Line 365, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_tl_intg_err/latest/run.log
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))'
UVM_ERROR @ 77426799 ps: (i2c_fsm.sv:1366) [ASSERT FAILED] SclSdaChangeNotSimultaneous_A
UVM_INFO @ 77426799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 1 failures:
34.i2c_target_stress_all_with_rand_reset.57001012147633992753930572117831765192642818340750570959943665742450002634787
Line 350, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6551135104 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6551135104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
38.i2c_target_stress_all_with_rand_reset.84539443146517401512674880719348807130423497363411108444287784208849949012912
Line 361, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10661474133 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (73 [0x49] vs 87 [0x57])
UVM_INFO @ 10661474133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---