I2C Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	3.282m	5.983ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	48.000s	1.773ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.730s	23.950us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.750s	41.837us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.430s	2.550ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.300s	62.178us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.370s	29.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.750s	41.837us	20	20	100.00
		i2c_csr_aliasing	1.300s	62.178us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.200s	47.722us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	56.825m	163.819ms	30	50	60.00
V2	host_perf	i2c_host_perf	15.355m	50.124ms	49	50	98.00
V2	host_override	i2c_host_override	0.680s	26.758us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	14.091m	37.371ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	15.732m	6.487ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.160s	1.073ms	50	50	100.00
		i2c_host_fifo_fmt_empty	39.860s	742.311us	50	50	100.00
		i2c_host_fifo_reset_rx	17.280s	295.928us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	5.886m	6.043ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	1.020m	2.779ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	5.305m	5.428ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.725m	13.594ms	49	50	98.00
V2	target_error_intr	i2c_target_unexp_stop	10.130s	2.512ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	5.220s	4.203ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	51.755m	29.891ms	38	50	76.00
V2	target_perf	i2c_target_perf	6.300s	1.027ms	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	3.424m	11.349ms	49	50	98.00
V2	target_fifo_empty	i2c_target_stress_rd	1.498m	12.775ms	50	50	100.00
		i2c_target_intr_smoke	8.350s	44.404ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.343m	10.148ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.611m	10.096ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	50.991m	43.451ms	45	50	90.00
		i2c_target_stress_rd	1.498m	12.775ms	50	50	100.00
		i2c_target_intr_stress_wr	32.390m	65.631ms	47	50	94.00
V2	target_timeout	i2c_target_timeout	9.130s	2.642ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	54.573m	36.128ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	6.160s	9.876ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.480s	810.981us	49	50	98.00
V2	alert_test	i2c_alert_test	0.680s	18.898us	50	50	100.00
V2	intr_test	i2c_intr_test	0.730s	43.563us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.750s	460.631us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.750s	460.631us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.730s	23.950us	5	5	100.00
		i2c_csr_rw	0.750s	41.837us	20	20	100.00
		i2c_csr_aliasing	1.300s	62.178us	5	5	100.00
		i2c_same_csr_outstanding	1.030s	41.915us	17	20	85.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.730s	23.950us	5	5	100.00
		i2c_csr_rw	0.750s	41.837us	20	20	100.00
		i2c_csr_aliasing	1.300s	62.178us	5	5	100.00
		i2c_same_csr_outstanding	1.030s	41.915us	17	20	85.00
V2		TOTAL			1439	1492	96.45
V2S	tl_intg_err	i2c_tl_intg_err	1.870s	613.027us	20	20	100.00
		i2c_sec_cm	0.950s	122.351us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.870s	613.027us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.976m	22.279ms	6	50	12.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	14.667m	30.614ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			6	100	6.00
		TOTAL			1625	1772	91.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	22	68.75
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.88	99.17	96.65	100.00	98.26	98.24	100.00	92.86

Failure Buckets

• Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 92 failures:

  • Test i2c_host_stress_all_with_rand_reset has 44 failures.

    • 0.i2c_host_stress_all_with_rand_reset.16137342401590539851907656712744332202111051348185588185139010841575349968386
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d79fa9dd-927a-4706-93d6-05f69ebb54f6
      

    • 1.i2c_host_stress_all_with_rand_reset.84629447507491697858096153322011340312858909725454358715498664598822962953968
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:238b4609-df14-4778-bc08-bc625552a3ac
      

    • ... and 42 more failures.

  • Test i2c_host_stress_all has 20 failures.

    • 3.i2c_host_stress_all.103399855855243067653024549094793973716841274405232953761132759462265226595207
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

        Job ID: smart:80a27d3f-f13c-4737-8a57-8f9fcef7b1ad
      

    • 7.i2c_host_stress_all.6804857660191485479965222835541001627863077852406482901918181849835373914659
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

        Job ID: smart:d0026fd1-c3a1-4752-ba0d-8798689459d9
      

    • ... and 18 more failures.

  • Test i2c_target_stress_all_with_rand_reset has 3 failures.

    • 3.i2c_target_stress_all_with_rand_reset.85975500057035943088327279069154204000887113179325147426509469992176235551914
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:55716f83-b10a-4b7d-a432-67a50ef4b6ac
      

    • 13.i2c_target_stress_all_with_rand_reset.80912660366591800032339301010836275059614077777976682351043355447494533725404
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:ace46445-c01d-4d1d-8e86-592498f65a8f
      

    • ... and 1 more failures.

  • Test i2c_target_stress_wr has 5 failures.

    • 8.i2c_target_stress_wr.77337976567162399424610520262167861205791417496135531293685776157099818225862
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_wr/latest/run.log

        Job ID: smart:9dd18c9a-38b5-4daf-86e6-d5d129ae8992
      

    • 9.i2c_target_stress_wr.87693285911163070131995727173211051744504671525837627543346191413887770471672
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_wr/latest/run.log

        Job ID: smart:cb2e651c-6c14-4cb5-88e4-b6d808bc4cc7
      

    • ... and 3 more failures.

  • Test i2c_target_stress_all has 12 failures.

    • 9.i2c_target_stress_all.89001717021783059436306178498270262335834135089695366197835085449225953937264
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log

        Job ID: smart:d3e0c74c-4406-4cb9-a6bf-e6e5e4c92544
      

    • 13.i2c_target_stress_all.78870364071043205762411546463103339027650337971652853343320434388978493351817
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log

        Job ID: smart:4bf1240e-c826-4251-b3c1-dab46b2ddec5
      

    • ... and 10 more failures.

  • ... and 3 more tests.

• UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 14 failures:

  • Test i2c_target_stress_all_with_rand_reset has 14 failures.

    • 6.i2c_target_stress_all_with_rand_reset.89998254110473501032803879022668551878443031336501197046136198839154160217988
      Line 413, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30614258768 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 17 [0x11])
        UVM_INFO @ 30614258768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.i2c_target_stress_all_with_rand_reset.18307303235443340862414683132621376716504787275159347199049367285892457396656
      Line 359, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36794070480 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 35 [0x23])
        UVM_INFO @ 36794070480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 13 failures:

  • Test i2c_target_stress_all_with_rand_reset has 13 failures.

    • 0.i2c_target_stress_all_with_rand_reset.3009891572520004387141635555686558349943920913107642063140348095486164652927
      Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107474577986 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 107474577986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.i2c_target_stress_all_with_rand_reset.25261099680547006452390097874666368145283340761189149680366378751795357877022
      Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   7812905 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
        UVM_INFO @   7812905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 9 failures:

  • Test i2c_target_stress_all_with_rand_reset has 9 failures.

    • 14.i2c_target_stress_all_with_rand_reset.107417519288031818103302804403283823405506890875246894347349374383104841280987
      Line 285, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3594381674 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xa1812894) == 0x0
        UVM_INFO @ 3594381674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.i2c_target_stress_all_with_rand_reset.78311660609433237956328023213145030102806098006147098751802460784765159254975
      Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1232321138 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x366e94) == 0x0
        UVM_INFO @ 1232321138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:

  • Test i2c_target_stress_all_with_rand_reset has 6 failures.

    • 2.i2c_target_stress_all_with_rand_reset.108521274360830948457411872979658452924795998788488450180364927303608994226192
      Line 307, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3975864550 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (112 [0x70] vs 118 [0x76])
        UVM_INFO @ 3975864550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.i2c_target_stress_all_with_rand_reset.30660311310573280952615097163890170676997453673558747106577445849129447657514
      Line 346, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7542946398 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (126 [0x7e] vs 225 [0xe1])
        UVM_INFO @ 7542946398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (cip_base_vseq.sv:483) [i2c_common_vseq] Check failed data == * (* [*] vs * [*]) has 2 failures:

  • Test i2c_same_csr_outstanding has 2 failures.

    • 9.i2c_same_csr_outstanding.104287556395563650078961351733963132401265025875602618444145351715618606501050
      Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log

        UVM_ERROR @  46697967 ps: (cip_base_vseq.sv:483) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data == 0 (64 [0x40] vs 0 [0x0])
        UVM_INFO @  46697967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.i2c_same_csr_outstanding.42055280551800590358260165251834101638624876724786973462134298890391756573434
      Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest/run.log

        UVM_ERROR @  10944127 ps: (cip_base_vseq.sv:483) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data == 0 (64 [0x40] vs 0 [0x0])
        UVM_INFO @  10944127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'scl_i' has 2 failures:

  • Test i2c_target_stress_all_with_rand_reset has 2 failures.

    • 10.i2c_target_stress_all_with_rand_reset.81549837369296174745669732604374207033001256206822447020243549305815664169679
      Line 355, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log

            Offending 'scl_i'
        UVM_ERROR @ 28836944558 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
        UVM_INFO @ 28836944558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 39.i2c_target_stress_all_with_rand_reset.114330977168694331738085040698198153715707102329062431825554631490344646353274
      Line 352, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_all_with_rand_reset/latest/run.log

            Offending 'scl_i'
        UVM_ERROR @ 6643958534 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
        UVM_INFO @ 6643958534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 2 failures:

  • Test i2c_target_stress_all_with_rand_reset has 2 failures.

    • 33.i2c_target_stress_all_with_rand_reset.27742501653991456109823624434811825631415206532942224328963342140850980711298
      Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 428590397 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
        UVM_INFO @ 428590397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.i2c_target_stress_all_with_rand_reset.24145642686563165906511387570488644220404762443618494316284940209385949433775
      Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1329294452 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
        UVM_INFO @ 1329294452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job i2c-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test i2c_same_csr_outstanding has 1 failures.

    • 13.i2c_same_csr_outstanding.45979995557754352751189466783321184989851503760562980593817122317334358484476
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest/run.log

        Job ID: smart:fc9c5132-b60d-4d66-ab61-809659c5c5a8
      

• Job i2c-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test i2c_target_intr_stress_wr has 1 failures.

    • 22.i2c_target_intr_stress_wr.36577611820247651336485781130996611291143693868686917029068734022439570399520
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest/run.log

        Job ID: smart:7d6a1e13-0190-4ea5-8fbb-8cfbc7730bc4
      

• UVM_ERROR (i2c_scoreboard.sv:698) scoreboard [scoreboard] has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 22.i2c_host_mode_toggle.957249006563642175273810927872807434439981734214770873906017871452832811395
      Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 210157680 ps: (i2c_scoreboard.sv:698) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
        direction  READ item mismatch!
        --> EXP:
        -----------------------------------------------
        Name              Type          Size  Value
      

• Job i2c-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test i2c_target_intr_stress_wr has 1 failures.

    • 25.i2c_target_intr_stress_wr.3174008815480680215145811593787274239195256862172646427238300529805942126109
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest/run.log

        Job ID: smart:29afbdf8-b59b-4838-aaca-32cda601d37b
      

• UVM_ERROR (i2c_scoreboard.sv:791) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 32.i2c_target_stress_all_with_rand_reset.99557744283700837805079888431238160438896651693655631400120336203822833133731
      Line 349, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10046105760 ps: (i2c_scoreboard.sv:791) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (81 [0x51] vs 65 [0x41])
        UVM_INFO @ 10046105760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:154) [i2c_target_hrst_vseq] timed out waiting for target_mode_wr_exp_fifo size:* has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 35.i2c_target_hrst.63018473607255055986668211349704691961258064932160963201269310364910379838685
      Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 11055092848 ps: (i2c_target_hrst_vseq.sv:154) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] timed out waiting for target_mode_wr_exp_fifo size:3
        UVM_INFO @ 11055092848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job i2c-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test i2c_target_tx_ovf has 1 failures.

    • 42.i2c_target_tx_ovf.25960085892527814185752627197732092151643042024745374024279274614061229733430
      Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_tx_ovf/latest/run.log

        Job ID: smart:1dc594d9-302d-4aa6-a6d9-c7b6438ed33a
      

Past Results

• Latest
• lint
• 2024.01.22_10.54.47
• 2024.01.18_08.34.16
• 2024.01.15_03.51.51
• 2024.01.11_03.06.27
• 2024.01.08_02.53.26
• 2024.01.04_01.17.41