I2C Simulation Results

Wednesday January 31 2024 20:02:52 UTC

GitHub Revision: 4ddd81322f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 21932966400645871531253577545734825173576945735198195365995401811578215479543

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 0 50 0.00
V1 target_smoke i2c_target_smoke 0 50 0.00
V1 csr_hw_reset i2c_csr_hw_reset 0 5 0.00
V1 csr_rw i2c_csr_rw 0 20 0.00
V1 csr_bit_bash i2c_csr_bit_bash 0 5 0.00
V1 csr_aliasing i2c_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 0 20 0.00
i2c_csr_aliasing 0 5 0.00
V1 TOTAL 0 155 0.00
V2 host_error_intr i2c_host_error_intr 0 50 0.00
V2 host_stress_all i2c_host_stress_all 0 50 0.00
V2 host_perf i2c_host_perf 0 50 0.00
V2 host_override i2c_host_override 0 50 0.00
V2 host_fifo_watermark i2c_host_fifo_watermark 0 50 0.00
V2 host_fifo_overflow i2c_host_fifo_overflow 0 50 0.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 0 50 0.00
i2c_host_fifo_fmt_empty 0 50 0.00
i2c_host_fifo_reset_rx 0 50 0.00
V2 host_fifo_full i2c_host_fifo_full 0 50 0.00
V2 host_timeout i2c_host_stretch_timeout 0 50 0.00
V2 host_rx_oversample i2c_host_rx_oversample 0 50 0.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 0 50 0.00
V2 target_error_intr i2c_target_unexp_stop 0 50 0.00
V2 target_glitch i2c_target_glitch 0 2 0.00
V2 target_stress_all i2c_target_stress_all 0 50 0.00
V2 target_perf i2c_target_perf 0 50 0.00
V2 target_fifo_overflow i2c_target_tx_ovf 0 50 0.00
V2 target_fifo_empty i2c_target_stress_rd 0 50 0.00
i2c_target_intr_smoke 0 50 0.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 0 50 0.00
i2c_target_fifo_reset_tx 0 50 0.00
V2 target_fifo_full i2c_target_stress_wr 0 50 0.00
i2c_target_stress_rd 0 50 0.00
i2c_target_intr_stress_wr 0 50 0.00
V2 target_timeout i2c_target_timeout 0 50 0.00
V2 target_clock_stretch i2c_target_stretch 0 50 0.00
V2 bad_address i2c_target_bad_addr 0 50 0.00
V2 target_mode_glitch i2c_target_hrst 0 50 0.00
V2 alert_test i2c_alert_test 0 50 0.00
V2 intr_test i2c_intr_test 0 50 0.00
V2 tl_d_oob_addr_access i2c_tl_errors 0 20 0.00
V2 tl_d_illegal_access i2c_tl_errors 0 20 0.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 0 5 0.00
i2c_csr_rw 0 20 0.00
i2c_csr_aliasing 0 5 0.00
i2c_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access i2c_csr_hw_reset 0 5 0.00
i2c_csr_rw 0 20 0.00
i2c_csr_aliasing 0 5 0.00
i2c_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 1492 0.00
V2S tl_intg_err i2c_tl_intg_err 0 20 0.00
i2c_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 0 20 0.00
V2S TOTAL 0 25 0.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 0 50 0.00
V3 target_loopback 0 0 --
V3 TOTAL 0 100 0.00
TOTAL 0 1772 0.00

Testplan Progress

Items Total Written Passing Progress
V1 7 7 0 0.00
V2 32 32 0 0.00
V2S 2 2 0 0.00
V3 3 2 0 0.00

Failure Buckets

Past Results