5c87d18988| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.914m | 6.065ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 48.030s | 17.703ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.740s | 58.364us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.740s | 58.854us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.540s | 900.822us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.300s | 223.280us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.170s | 46.385us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.740s | 58.854us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.300s | 223.280us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.100s | 153.827us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.255m | 50.748ms | 34 | 50 | 68.00 |
| V2 | host_perf | i2c_host_perf | 53.454m | 49.097ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.680s | 16.985us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 14.361m | 7.004ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 14.962m | 6.880ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.250s | 622.802us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 43.450s | 1.588ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.400s | 1.078ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 6.130m | 13.536ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 55.500s | 17.095ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 5.335m | 12.843ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 3.191m | 2.151ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 10.050s | 2.296ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.070s | 848.200us | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 51.876m | 38.788ms | 43 | 50 | 86.00 |
| V2 | target_perf | i2c_target_perf | 5.380s | 1.812ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 4.634m | 3.571ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.569m | 44.752ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.330s | 4.259ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.232m | 10.125ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.750m | 10.064ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 58.560m | 54.472ms | 48 | 50 | 96.00 |
| i2c_target_stress_rd | 1.569m | 44.752ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 17.312m | 22.016ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 9.800s | 2.404ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 52.861m | 19.416ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.130s | 1.490ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.520s | 999.883us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 17.472us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 20.476us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.670s | 145.849us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.670s | 145.849us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.740s | 58.364us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.740s | 58.854us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.300s | 223.280us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.070s | 97.053us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.740s | 58.364us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.740s | 58.854us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.300s | 223.280us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.070s | 97.053us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1463 | 1492 | 98.06 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.970s | 410.705us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.970s | 603.894us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.970s | 410.705us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 19.226m | 37.866ms | 2 | 50 | 4.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.832m | 18.129ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 2 | 100 | 2.00 | |||
| TOTAL | 1645 | 1772 | 92.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 32 | 32 | 27 | 84.38 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.73 | 99.27 | 96.92 | 100.00 | 96.52 | 98.57 | 100.00 | 92.86 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 79 failures:
Test i2c_host_stress_all_with_rand_reset has 47 failures.
1.i2c_host_stress_all_with_rand_reset.39978285860733631555492193292730226161196070727862000375343257493122071709688
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:df996cb6-1afa-4e48-b382-e362832202c8
2.i2c_host_stress_all_with_rand_reset.57066085047280682989462062344606178838975132565710186352880730017123866880214
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e2c609df-10fe-48dc-9fe3-cdf1ad5ff366
... and 45 more failures.
Test i2c_target_stress_all has 7 failures.
2.i2c_target_stress_all.114661923693843885763606917136045292128065126432695249261766281129121714248414
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
Job ID: smart:ed7f8df9-6a73-4a35-b5fa-fa666486e45c
9.i2c_target_stress_all.96281302558373750710907721979386368204611906289531421738529722389829497009171
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
Job ID: smart:63a2b454-7ba3-4e9c-92b2-a9b904e07362
... and 5 more failures.
Test i2c_host_stress_all has 16 failures.
5.i2c_host_stress_all.37719370438172064607532788277073797768443192770447166007097607181904699644722
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:8fe9a70d-6b65-4e94-9801-a3daff619d9a
8.i2c_host_stress_all.79408414191859110742215155328623242380016922624915401877109060372203087345643
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
Job ID: smart:453833f2-b080-43f9-9e65-ce1f95f57e55
... and 14 more failures.
Test i2c_target_stress_wr has 2 failures.
16.i2c_target_stress_wr.25913615015581303428536330828771655904812178974493018195829381543209042650260
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_wr/latest/run.log
Job ID: smart:eab98686-898f-4237-9c06-42afbf986786
19.i2c_target_stress_wr.58566938182206820599958018788192795693133729171078453574501507673595313886220
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_wr/latest/run.log
Job ID: smart:1df99a77-7df4-44a1-8baf-bda55ce94065
Test i2c_target_stretch has 3 failures.
19.i2c_target_stretch.39407640174705384905838706335551500118938525784981470077716802525175013211964
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
Job ID: smart:88380729-1d11-49ad-a63e-35f4315ec4d6
26.i2c_target_stretch.33846419531898003363497407885716741994632747832667714458583521102929366331171
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stretch/latest/run.log
Job ID: smart:e50f5b32-1d72-4789-b11c-f88968ba931a
... and 1 more failures.
... and 1 more tests.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 13 failures:
1.i2c_target_stress_all_with_rand_reset.248312178501847687367481884302407418116843745045034708833363238066101275245
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32362389 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 5 [0x5])
UVM_INFO @ 32362389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.77864580135636820787109710660247213999556240332968058298117364308224303472290
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8340830025 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 12 [0xc])
UVM_INFO @ 8340830025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 10 failures:
0.i2c_target_stress_all_with_rand_reset.26809580529669756923957677714877219915295389983596001957157009989964468675305
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 116389621 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 116389621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.105147617892678503377490272731463215481041858840482792697203277345534334050878
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3219860213 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 3219860213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 9 failures:
6.i2c_target_stress_all_with_rand_reset.34722191091190822541833932342109722279514662523725804227430569367819990480235
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9224620583 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 9224620583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.115354226100767612847743899755006847817448307581279431797902723587367989267585
Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4049449799 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 4049449799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 9 failures:
10.i2c_target_stress_all_with_rand_reset.55744885251567184821938723901289723903261784124012779501898767511809124414745
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1545292721 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xafeb3694) == 0x0
UVM_INFO @ 1545292721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all_with_rand_reset.12921167250630397493644676366578573100609078778673313259329676481386979722638
Line 515, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 64068656394 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x12667c94) == 0x0
UVM_INFO @ 64068656394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Offending 'scl_i' has 3 failures:
4.i2c_target_stress_all_with_rand_reset.53510900363154668937357863877018151960940372462045702698838060372635001732652
Line 438, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 18128945459 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 18128945459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_target_stress_all_with_rand_reset.115260219903784217408913187186558628591608366780683742111678378182995061260659
Line 455, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 43905512608 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 43905512608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
14.i2c_target_stress_all_with_rand_reset.48013485722608595925916605274418121113759120816069324435551993171192710750882
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3354076605 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (112 [0x70] vs 140 [0x8c])
UVM_INFO @ 3354076605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_stress_all_with_rand_reset.46460932861462598606617896511740276277020855880904590760076759509190540023208
Line 450, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12345297888 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (166 [0xa6] vs 4 [0x4])
UVM_INFO @ 12345297888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
9.i2c_target_bad_addr.113814173487877417619378753442111411831080464287804698692040029823987341193705
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:56) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
45.i2c_host_stress_all_with_rand_reset.101312845779287771469500628051226127251022735198319190470999247621945811157337
Line 17741, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17336172797 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 17336172797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---