I2C Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	2.639m	10.628ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	48.250s	1.920ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	70.898us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.740s	39.485us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.070s	1.257ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.360s	396.715us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	3.230s	381.336us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.740s	39.485us	20	20	100.00
		i2c_csr_aliasing	1.360s	396.715us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.350s	50.043us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	52.939m	57.947ms	35	50	70.00
V2	host_perf	i2c_host_perf	22.110m	28.928ms	50	50	100.00
V2	host_override	i2c_host_override	0.690s	20.766us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	13.921m	6.705ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	17.576m	26.576ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.230s	170.492us	50	50	100.00
		i2c_host_fifo_fmt_empty	38.370s	716.265us	50	50	100.00
		i2c_host_fifo_reset_rx	14.590s	1.303ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	5.595m	25.666ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	58.900s	6.393ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	6.463m	10.508ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.612m	4.534ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	9.270s	6.679ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	5.450s	2.413ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	57.637m	50.750ms	39	50	78.00
V2	target_perf	i2c_target_perf	5.720s	920.367us	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	6.186m	17.154ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.804m	20.104ms	50	50	100.00
		i2c_target_intr_smoke	8.050s	6.723ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.438m	10.057ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.635m	10.104ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	56.126m	52.387ms	46	50	92.00
		i2c_target_stress_rd	1.804m	20.104ms	50	50	100.00
		i2c_target_intr_stress_wr	24.161m	27.193ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	8.970s	7.663ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	55.497m	39.938ms	42	50	84.00
V2	bad_address	i2c_target_bad_addr	6.970s	8.204ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	3.770s	3.629ms	50	50	100.00
V2	alert_test	i2c_alert_test	0.690s	71.724us	50	50	100.00
V2	intr_test	i2c_intr_test	0.730s	30.993us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.600s	831.306us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.600s	831.306us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	70.898us	5	5	100.00
		i2c_csr_rw	0.740s	39.485us	20	20	100.00
		i2c_csr_aliasing	1.360s	396.715us	5	5	100.00
		i2c_same_csr_outstanding	0.990s	44.334us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	70.898us	5	5	100.00
		i2c_csr_rw	0.740s	39.485us	20	20	100.00
		i2c_csr_aliasing	1.360s	396.715us	5	5	100.00
		i2c_same_csr_outstanding	0.990s	44.334us	20	20	100.00
V2		TOTAL			1452	1492	97.32
V2S	tl_intg_err	i2c_tl_intg_err	1.940s	397.851us	20	20	100.00
		i2c_sec_cm	0.970s	132.842us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.940s	397.851us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.939m	60.955ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.447m	16.093ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1632	1772	92.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	26	81.25
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.04	99.07	96.52	100.00	93.04	98.13	100.00	92.54

Failure Buckets

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 48 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_target_stress_all_with_rand_reset.86364850933566415623125960432008231483542599448817029563981979751326894976982
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:de293ea8-b6ce-4642-af19-a6574a6c6157
```
  - 21.i2c_target_stress_all_with_rand_reset.106459896238409889352202782572196678413587345776592166006081145525593324268325
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e27adf46-603c-4b79-864c-99e296a24b6e
```
- Test i2c_target_stretch has 8 failures.
  - 1.i2c_target_stretch.81141416152138672872820167711626641473687210131943739531902274992364961897776
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
```
  Job ID: smart:f73658c4-3387-4795-af80-64d3c6fcea67
```
  - 14.i2c_target_stretch.3410519120770989726118586845597670938276602054026426607204060120703972923825
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stretch/latest/run.log
```
  Job ID: smart:33ad1d9b-7663-4792-8e27-a64560f7e3c9
```
  - ... and 6 more failures.
- Test i2c_target_stress_all has 11 failures.
  - 1.i2c_target_stress_all.90906369817882026891520200830383926562871268957253732462960199718810519942641
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:a2ffea0a-3f38-4b21-be0f-3f83982bcfe1
```
  - 2.i2c_target_stress_all.92703871940321638509337953278008649907668228269152514614889366661370335238768
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:5a5831d5-1224-4f45-bc35-5b5d010df8ed
```
  - ... and 9 more failures.
- Test i2c_host_stress_all has 15 failures.
  - 2.i2c_host_stress_all.105484395772451185446486765164785510121331537973727053633251155021110018862414
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:af8a73e3-5896-4565-bbfc-fe7a5fe49d91
```
  - 6.i2c_host_stress_all.26532171693107460502540160183033401124172912517112886173710725815316625468598
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:dbc57aea-1a9c-4612-b498-6f8fd6adbf4d
```
  - ... and 13 more failures.
- Test i2c_target_stress_wr has 4 failures.
  - 11.i2c_target_stress_wr.30304303217961994797308184429701700428846557986401078599551120748390310358538
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:f6b0fcd8-d1d0-49b2-8fff-bca2b9badc07
```
  - 35.i2c_target_stress_wr.112701638971286533032461609330540394767442287258587535381770091745806401429020
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:dfe05d8f-5bd3-48a1-a140-6b47bd8a3122
```
  - ... and 2 more failures.
- ... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:756) [i2c_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 43 failures:

Test i2c_host_stress_all_with_rand_reset has 38 failures.

0.i2c_host_stress_all_with_rand_reset.32581920500144442223704909315439429197259027711325426860307980511383819312832
Line 1326, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3685626067 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 3685626067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.27349198544433982160128991933527981158194991475554545368962620165896069436441
Line 6293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 60955144372 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 60955144372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 36 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

7.i2c_target_stress_all_with_rand_reset.26691184666571762047574553852208252346097328008823103294295194074275513028449
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 580859586 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 580859586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.i2c_target_stress_all_with_rand_reset.67003918501377773681807865218585467110674505046216531370561954213479944817190
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 103850274 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 103850274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:714) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 25 failures:
- Test i2c_target_stress_all_with_rand_reset has 20 failures.
  - 3.i2c_target_stress_all_with_rand_reset.82387433701002133254388799658126344581103458556471234342315483858234919303763
    Line 327, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9371370566 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9371370566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_all_with_rand_reset.47744570728459826317223184206347412827400450866444293915415146006411667006064
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 500620940 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 500620940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
- Test i2c_host_stress_all_with_rand_reset has 5 failures.
  - 20.i2c_host_stress_all_with_rand_reset.22761656548205032035983007851063795969236967235837842158973161440482038262619
    Line 6416, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7828492142 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7828492142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.i2c_host_stress_all_with_rand_reset.67346810648520868203284053483600420721503637467966517498442106196779687993032
    Line 8698, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17297868052 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17297868052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 15 failures:
- Test i2c_target_stress_all_with_rand_reset has 15 failures.
  - 1.i2c_target_stress_all_with_rand_reset.60391879915035668361456923430244696666471177796223006661497970616310104709922
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5658204073 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xfbd9ee14) == 0x0
  UVM_INFO @ 5658204073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_stress_all_with_rand_reset.109981897017742785909968717050399741581532544568037773904834924853397771034917
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 540006133 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xe7ccff94) == 0x0
  UVM_INFO @ 540006133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 5.i2c_target_stress_all_with_rand_reset.27601394861127974437411802309793577734706718690030450417632166169556323460225
    Line 430, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16755444591 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 16755444591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_stress_all_with_rand_reset.19678109434937565619053146106015741025148499353969844609800722765237107590846
    Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4585449208 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 4585449208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending 'scl_i' has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 11.i2c_target_stress_all_with_rand_reset.5038703583772468459815089351640192851305643441978481490809016951740062217726
    Line 448, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 16093394014 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 16093394014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 45.i2c_target_stress_all_with_rand_reset.101931087601424082974133145394167052017781386055009129657930526670801859549682
    Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 2266943110 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 2266943110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.97774023229264097509214634870047587840021946916294643906523022523481102933950
    Line 367, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35536692785 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (148 [0x94] vs 5 [0x5])
  UVM_INFO @ 35536692785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 41.i2c_target_bad_addr.110203869015292351288810137759433625112102790572356335880063983384277559241165
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```