I2C Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	2.506m	10.600ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	54.330s	2.065ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.740s	49.255us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.760s	73.608us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.150s	3.415ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.280s	1.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.380s	106.428us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.760s	73.608us	20	20	100.00
		i2c_csr_aliasing	1.280s	1.106ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.020s	89.024us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	58.587m	49.292ms	35	50	70.00
V2	host_perf	i2c_host_perf	40.537m	52.146ms	50	50	100.00
V2	host_override	i2c_host_override	0.710s	21.026us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	13.030m	12.784ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	15.423m	25.212ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.150s	597.347us	50	50	100.00
		i2c_host_fifo_fmt_empty	31.520s	3.012ms	50	50	100.00
		i2c_host_fifo_reset_rx	17.480s	1.135ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	5.268m	3.393ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	52.240s	2.441ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	5.834m	31.248ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.155m	2.946ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	9.100s	1.941ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	4.640s	19.228ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	54.736m	54.483ms	37	50	74.00
V2	target_perf	i2c_target_perf	5.570s	988.527us	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	4.526m	15.567ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.810m	2.435ms	50	50	100.00
		i2c_target_intr_smoke	8.630s	2.104ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.351m	10.096ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.554m	10.086ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	55.031m	48.032ms	43	50	86.00
		i2c_target_stress_rd	1.810m	2.435ms	50	50	100.00
		i2c_target_intr_stress_wr	25.320m	27.778ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.100s	6.786ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	44.830m	32.448ms	40	50	80.00
V2	bad_address	i2c_target_bad_addr	6.140s	7.305ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.410s	752.209us	49	50	98.00
V2	alert_test	i2c_alert_test	0.710s	19.582us	50	50	100.00
V2	intr_test	i2c_intr_test	0.730s	57.490us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.090s	639.846us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.090s	639.846us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.740s	49.255us	5	5	100.00
		i2c_csr_rw	0.760s	73.608us	20	20	100.00
		i2c_csr_aliasing	1.280s	1.106ms	5	5	100.00
		i2c_same_csr_outstanding	1.180s	46.827us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.740s	49.255us	5	5	100.00
		i2c_csr_rw	0.760s	73.608us	20	20	100.00
		i2c_csr_aliasing	1.280s	1.106ms	5	5	100.00
		i2c_same_csr_outstanding	1.180s	46.827us	20	20	100.00
V2		TOTAL			1446	1492	96.92
V2S	tl_intg_err	i2c_tl_intg_err	2.000s	130.933us	20	20	100.00
		i2c_sec_cm	0.990s	292.743us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.000s	130.933us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.489m	55.012ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	14.148m	37.575ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1626	1772	91.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	27	84.38
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.07	99.07	96.52	100.00	93.04	98.13	100.00	92.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 66 failures:

Test i2c_host_stress_all_with_rand_reset has 45 failures.

0.i2c_host_stress_all_with_rand_reset.63185734733517871848636612274309032396991785143712003585140381310182881014275
Line 5071, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 91649464103 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 91649464103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.86158958087292584628080013908016009662087029846543092142874136009668801569468
Line 2408, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5966104562 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 5966104562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 43 more failures.

Test i2c_target_stress_all_with_rand_reset has 21 failures.

1.i2c_target_stress_all_with_rand_reset.92530812815450630515187399752189618722625447829599114540052600596110144263770
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 192281935 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 192281935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.86927007684526070436272407789358972749219705715054361096417171772712495272672
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 102068447 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 102068447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 19 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 50 failures:
- Test i2c_target_stretch has 10 failures.
  - 0.i2c_target_stretch.98943141976441414810343492233552425148826579144820300755762738507142991524378
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  Job ID: smart:71d4d18b-e714-4753-a2cd-18aff84af219
```
  - 1.i2c_target_stretch.54668141557269457059227978323253380807758279478112920188466775474635012438973
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
```
  Job ID: smart:c3936bce-4ddc-482e-9fbd-4e6fbb9706eb
```
  - ... and 8 more failures.
- Test i2c_host_stress_all has 15 failures.
  - 1.i2c_host_stress_all.104026056903735997380243003260257466659317079175196472605386663219986170334254
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:eb2c5e19-eb03-4051-9943-13dbd4cab312
```
  - 2.i2c_host_stress_all.23065365766671993243167139350170066728323721911095688245140283466558286078890
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:b18357dd-4da2-4137-a4a2-39b49a3c58bc
```
  - ... and 13 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 3.i2c_host_stress_all_with_rand_reset.105815613817365208736427285010997884541429116768184480654028532483633333558207
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7cb3e02f-3be2-454e-89af-aa723ad79335
```
  - 12.i2c_host_stress_all_with_rand_reset.60340504830912449523412078367746741927794273468990561020628746366341936207598
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:be953617-9cbb-4a07-b781-8315b13e0f5c
```
  - ... and 2 more failures.
- Test i2c_target_stress_wr has 7 failures.
  - 4.i2c_target_stress_wr.14121654622597605349206361430848052405656117432713810423630494720862455346165
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:428cf096-a98a-4b3f-9d5b-e5c6caab58a5
```
  - 8.i2c_target_stress_wr.25982913935120831688834203487043848451686744830366773247204618762348421448563
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:6e9f531b-9dc2-4913-9d9e-d0bcee6bcc5e
```
  - ... and 5 more failures.
- Test i2c_target_stress_all has 13 failures.
  - 4.i2c_target_stress_all.94795318469233444429571358943825931053591343121014518166422753227548768050683
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:c30a57ae-1830-4da3-b0df-59cf4c47f6be
```
  - 12.i2c_target_stress_all.22499594855614662751674210233653520099143981685415808699921601294936085463461
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:4ec9c806-2d17-4009-bf74-0fd41e1cf224
```
  - ... and 11 more failures.
- ... and 1 more tests.
UVM_ERROR (cip_base_vseq.sv:719) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 11 failures:
- Test i2c_target_stress_all_with_rand_reset has 11 failures.
  - 10.i2c_target_stress_all_with_rand_reset.54578732730342074002811098980878556036207637712865986024599014854493648952311
    Line 352, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30385487302 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 30385487302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.i2c_target_stress_all_with_rand_reset.71640202263996320928658733071312737086168864293216526392162375996688947515186
    Line 362, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7026894579 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7026894579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 9 failures:
- Test i2c_target_stress_all_with_rand_reset has 9 failures.
  - 0.i2c_target_stress_all_with_rand_reset.15304737364249988750527145699259526590419725224075726315702836081492606048656
    Line 288, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12944491389 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x37ad4394) == 0x0
  UVM_INFO @ 12944491389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all_with_rand_reset.98486143117592749098976967731032001989278913510692065168098298431352685762980
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1092375907 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x4caf8a14) == 0x0
  UVM_INFO @ 1092375907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 4.i2c_target_stress_all_with_rand_reset.19495727390076536467872074681210226700880958684126583363077875363452179348078
    Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4702945070 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 4702945070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.i2c_target_stress_all_with_rand_reset.32459905116774472281523834093134737539039364828947037850241239604219990834630
    Line 358, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9770938515 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 9770938515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 26.i2c_target_stress_all_with_rand_reset.113372997261525605655705932966753022603484060144021539712506884255201490291889
    Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127739854 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (112 [0x70] vs 80 [0x50])
  UVM_INFO @ 127739854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.i2c_target_stress_all_with_rand_reset.71029369206179283142116384328476003834984890802874438449941172480503021322215
    Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1529362753 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (226 [0xe2] vs 242 [0xf2])
  UVM_INFO @ 1529362753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_target_stress_all_with_rand_reset.105394627225657571146530011786668167423977859462847841785790735506613154291313
    Line 459, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16946764265 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (12 [0xc] vs 27 [0x1b])
  UVM_INFO @ 16946764265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:154) [i2c_target_hrst_vseq] timed out waiting for target_mode_wr_exp_fifo size:* has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 34.i2c_target_hrst.2180308065043469656817372806043928831198293549609076150788428406929654991336
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 12490625453 ps: (i2c_target_hrst_vseq.sv:154) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] timed out waiting for target_mode_wr_exp_fifo size:48
  UVM_INFO @ 12490625453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:56) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 37.i2c_host_stress_all_with_rand_reset.67219466344694022481976539501933447042863043255892735456575378936596765814485
    Line 11538, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55011733553 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 55011733553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_i' has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 42.i2c_target_stress_all_with_rand_reset.109712133278269857943619372743437727834142473973617291308269794825012936381752
    Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 1053321006 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 1053321006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```