I2C Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	2.741m	5.291ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	57.510s	6.487ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.730s	22.314us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.740s	23.165us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.860s	313.608us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.310s	60.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.530s	35.406us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.740s	23.165us	20	20	100.00
		i2c_csr_aliasing	1.310s	60.391us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	1.940s	45.928us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	57.151m	84.259ms	32	50	64.00
V2	host_perf	i2c_host_perf	29.989m	51.976ms	50	50	100.00
V2	host_override	i2c_host_override	0.710s	19.574us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	13.273m	27.328ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	16.901m	25.680ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.240s	206.209us	50	50	100.00
		i2c_host_fifo_fmt_empty	36.380s	625.719us	50	50	100.00
		i2c_host_fifo_reset_rx	16.720s	1.229ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	5.987m	3.968ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	1.052m	2.362ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	4.736m	5.997ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.008m	17.387ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	11.250s	7.378ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	4.350s	3.071ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	58.839m	62.377ms	45	50	90.00
V2	target_perf	i2c_target_perf	6.410s	1.030ms	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	4.470m	3.527ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.296m	1.882ms	50	50	100.00
		i2c_target_intr_smoke	8.770s	9.122ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.267m	10.133ms	49	50	98.00
		i2c_target_fifo_reset_tx	1.476m	10.129ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	55.888m	47.006ms	46	50	92.00
		i2c_target_stress_rd	1.296m	1.882ms	50	50	100.00
		i2c_target_intr_stress_wr	19.579m	24.310ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.730s	2.133ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	59.224m	42.366ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	7.250s	1.870ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.500s	1.418ms	50	50	100.00
V2	alert_test	i2c_alert_test	0.700s	43.043us	50	50	100.00
V2	intr_test	i2c_intr_test	0.750s	22.471us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.900s	1.492ms	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.900s	1.492ms	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.730s	22.314us	5	5	100.00
		i2c_csr_rw	0.740s	23.165us	20	20	100.00
		i2c_csr_aliasing	1.310s	60.391us	5	5	100.00
		i2c_same_csr_outstanding	1.090s	51.646us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.730s	22.314us	5	5	100.00
		i2c_csr_rw	0.740s	23.165us	20	20	100.00
		i2c_csr_aliasing	1.310s	60.391us	5	5	100.00
		i2c_same_csr_outstanding	1.090s	51.646us	20	20	100.00
V2		TOTAL			1460	1492	97.86
V2S	tl_intg_err	i2c_tl_intg_err	1.990s	431.984us	20	20	100.00
		i2c_sec_cm	0.950s	65.783us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.990s	431.984us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	17.046m	9.261ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	15.752m	221.633ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1640	1772	92.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	27	84.38
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.14	99.12	96.72	100.00	93.04	98.24	100.00	92.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 65 failures:

Test i2c_host_stress_all_with_rand_reset has 44 failures.

0.i2c_host_stress_all_with_rand_reset.3146670932182448994921378480661208605092899315299800216293962159129608371506
Line 7295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9261242316 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 9261242316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.10804836602361479871301383278897862626669317517163589209341378247310714742272
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10003616444 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 10003616444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 42 more failures.

Test i2c_target_stress_all_with_rand_reset has 21 failures.

3.i2c_target_stress_all_with_rand_reset.58718423534512105447830477493506015011720870304099341844004747395175594720907
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1474327037 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 1474327037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.86512186790732853229807957939308214200192217636585470712384503061064760008783
Line 336, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34346281508 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 34346281508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 19 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:
- Test i2c_target_stress_wr has 4 failures.
  - 0.i2c_target_stress_wr.92791816955752476822263516377935596458063888075531017917174514553499450551800
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:4810f2fc-8a35-4367-a4fa-299e83cbfb73
```
  - 5.i2c_target_stress_wr.102082530011733684864978831915025920086704922866151231435106090114552726594676
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:1d4cd659-e721-4c0d-b9c4-950649d0f87d
```
  - ... and 2 more failures.
- Test i2c_host_stress_all_with_rand_reset has 6 failures.
  - 2.i2c_host_stress_all_with_rand_reset.45500033949613833349818463799450238401733898063969211417454189743291992382013
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cb11e99e-4850-48e8-adee-6a2b7071fa9a
```
  - 17.i2c_host_stress_all_with_rand_reset.37392116752655325943027770361329838823545506862272046735831582019406009777511
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:25b0746d-9ad6-4a82-85a7-7c378acaedac
```
  - ... and 4 more failures.
- Test i2c_host_stress_all has 18 failures.
  - 3.i2c_host_stress_all.34158794703966405299664057264754247848659534559948755325232676437434547980344
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:e3a07ead-0e62-41f2-a4b5-adfa60213641
```
  - 4.i2c_host_stress_all.81335538684908438658411415070085462603253752329139876155217169243130762295665
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:59cb9298-6adc-44b9-bed9-431cffdc3c1d
```
  - ... and 16 more failures.
- Test i2c_target_stress_all has 5 failures.
  - 7.i2c_target_stress_all.79458598508312643161473062660168237157523113397608649849759362397784867099473
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:75867ec9-5243-4a5f-b88e-2cee1dfb339a
```
  - 17.i2c_target_stress_all.108726773706845758852214894947890682100196341546072699366335926366907401361622
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:bdee71a6-a231-4cd0-afae-095620bdb923
```
  - ... and 3 more failures.
- Test i2c_target_stretch has 4 failures.
  - 19.i2c_target_stretch.45250951124008767871711508105520555435431565888145844171601533049911491821039
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
```
  Job ID: smart:3b89cf42-5067-4000-b8a2-3328cf2f950b
```
  - 28.i2c_target_stretch.22521635729790770723296852775311102344785020050053849376941513613544548839605
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stretch/latest/run.log
```
  Job ID: smart:ed3234df-febd-44df-806b-5a603a47a8cd
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 14 failures:
- Test i2c_target_stress_all_with_rand_reset has 14 failures.
  - 1.i2c_target_stress_all_with_rand_reset.76668181562045471651475999161298232062375727842307887276881357087483133525171
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 993980293 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x1c393194) == 0x0
  UVM_INFO @ 993980293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.i2c_target_stress_all_with_rand_reset.9807867799303988378918518646639208204323715944392522216583851969926714560204
    Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5573746040 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xa18a6494) == 0x0
  UVM_INFO @ 5573746040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:719) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 7 failures:
- Test i2c_target_stress_all_with_rand_reset has 7 failures.
  - 2.i2c_target_stress_all_with_rand_reset.31666680624305199340194182640818435392826667956044101458970790594963328431006
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115355353 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 115355353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_stress_all_with_rand_reset.25552233595704622567037024482664986882629494283736549601043855050913104363570
    Line 338, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5990979707 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5990979707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 0.i2c_target_stress_all_with_rand_reset.68707060536550967150800690325363191741557634017457378947595603493606263111336
    Line 338, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28007699540 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 28007699540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_all_with_rand_reset.49880934342281962061189811797866845402295662304214584436507128202891385704006
    Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5374204468 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 5374204468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 15.i2c_target_stress_all_with_rand_reset.108158717399611828924804678728864244902045557872074597981920247510926105882946
    Line 350, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7871776729 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 7871776729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.i2c_target_stress_all_with_rand_reset.25203973988520185946986030324515715083010694914376331899743398250563310414415
    Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 400392364 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 2 [0x2])
  UVM_INFO @ 400392364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_fifo_reset_acq has 1 failures.
  - 4.i2c_target_fifo_reset_acq.12196894643828574099135892555342807820472039602688888564970709471939416305488
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 11.i2c_target_stress_all_with_rand_reset.71231347859785151367967334926448532595217544573354907024787842750472931101755
    Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1274205193 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (87 [0x57] vs 89 [0x59])
  UVM_INFO @ 1274205193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```