I2C Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	3.657m	5.907ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	45.550s	3.664ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	21.832us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.810s	104.523us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.790s	95.639us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.290s	107.032us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.620s	66.473us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	104.523us	20	20	100.00
		i2c_csr_aliasing	1.290s	107.032us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.180s	156.591us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	59.553m	71.327ms	29	50	58.00
V2	host_perf	i2c_host_perf	20.869m	26.214ms	49	50	98.00
V2	host_override	i2c_host_override	0.710s	20.584us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	12.846m	15.707ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	16.015m	67.077ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.170s	653.932us	50	50	100.00
		i2c_host_fifo_fmt_empty	50.130s	8.913ms	50	50	100.00
		i2c_host_fifo_reset_rx	16.060s	271.590us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	5.619m	3.547ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	55.990s	6.680ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	6.062m	2.713ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.510m	4.277ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	10.330s	8.324ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	4.510s	3.428ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	59.172m	50.598ms	41	50	82.00
V2	target_perf	i2c_target_perf	6.080s	4.086ms	50	50	100.00
V2	target_fifo_overflow	i2c_target_tx_ovf	3.444m	3.150ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.537m	2.291ms	50	50	100.00
		i2c_target_intr_smoke	9.030s	19.753ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.328m	10.043ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.599m	10.064ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	55.151m	48.789ms	45	50	90.00
		i2c_target_stress_rd	1.537m	2.291ms	50	50	100.00
		i2c_target_intr_stress_wr	46.637m	76.798ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.220s	2.134ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	43.999m	17.346ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	6.630s	2.714ms	48	50	96.00
V2	target_mode_glitch	i2c_target_hrst	3.730s	2.691ms	50	50	100.00
V2	alert_test	i2c_alert_test	0.710s	47.248us	50	50	100.00
V2	intr_test	i2c_intr_test	0.790s	16.413us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.600s	118.985us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.600s	118.985us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	21.832us	5	5	100.00
		i2c_csr_rw	0.810s	104.523us	20	20	100.00
		i2c_csr_aliasing	1.290s	107.032us	5	5	100.00
		i2c_same_csr_outstanding	1.030s	101.610us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	21.832us	5	5	100.00
		i2c_csr_rw	0.810s	104.523us	20	20	100.00
		i2c_csr_aliasing	1.290s	107.032us	5	5	100.00
		i2c_same_csr_outstanding	1.030s	101.610us	20	20	100.00
V2		TOTAL			1447	1492	96.98
V2S	tl_intg_err	i2c_tl_intg_err	2.200s	2.220ms	20	20	100.00
		i2c_sec_cm	0.970s	251.290us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.200s	2.220ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.171m	9.837ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	15.929m	33.128ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1627	1772	91.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	32	32	26	81.25
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.08	99.07	96.59	100.00	93.04	98.13	100.00	92.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 67 failures:

Test i2c_host_stress_all_with_rand_reset has 42 failures.

1.i2c_host_stress_all_with_rand_reset.68222093664983498644304258098561685243643638265108505372722532338669909803687
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 135060733 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 135060733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all_with_rand_reset.94402872926978883064255408181907374014875845389558022014719879114640619210222
Line 1796, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7819966950 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7819966950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 40 more failures.

Test i2c_target_stress_all_with_rand_reset has 25 failures.

1.i2c_target_stress_all_with_rand_reset.48777255975884220574256878112542102433873568642741399376422088921484116282960
Line 360, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5704194368 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5704194368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.70693048634636807613348057381914064673200344334438136129568418214862479019557
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7409861928 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7409861928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 52 failures:
- Test i2c_host_stress_all has 21 failures.
  - 0.i2c_host_stress_all.53136017846630594225141092012066498923296545945289747906836849139667888601641
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:468ea61c-55ac-4b19-97fa-1392ee58ac57
```
  - 7.i2c_host_stress_all.34209062212464975659170765641624449251056296273670269651020564721148134921977
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:11251a34-1ac2-48dd-b394-18e350b67887
```
  - ... and 19 more failures.
- Test i2c_target_stress_all has 9 failures.
  - 0.i2c_target_stress_all.75538832187088869952414865500794829676888956558050367828677700237665781602964
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:7e7070c5-afe9-40c6-a548-6c160e28dab3
```
  - 4.i2c_target_stress_all.65507698868846744781489249542103942643544253210670959176254618201239268276272
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:f42b5837-5ded-45b1-b6dc-86d05d9909a2
```
  - ... and 7 more failures.
- Test i2c_host_stress_all_with_rand_reset has 6 failures.
  - 0.i2c_host_stress_all_with_rand_reset.62571523956798238436611188893726980443758261482049883052175503597862819943744
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:028727b0-6382-4338-bccf-bfe7be0eab45
```
  - 5.i2c_host_stress_all_with_rand_reset.83702187539502608796717654397695146750809124954660286997035962388270594034409
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0a7538c6-934d-436a-88c8-440ad73d0c06
```
  - ... and 4 more failures.
- Test i2c_target_stretch has 7 failures.
  - 3.i2c_target_stretch.42881811337152902188114617181546114539486029857816532757182013609430226023292
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  Job ID: smart:c74e27b4-3837-4a8a-9f7c-4e5944f3f9a4
```
  - 9.i2c_target_stretch.10289513906826523500152844366325829729821108077260827244388814838266428678407
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
```
  Job ID: smart:4a6b0e8f-7b61-4829-8fec-789d5c612f32
```
  - ... and 5 more failures.
- Test i2c_target_stress_wr has 5 failures.
  - 12.i2c_target_stress_wr.43406189668197441283750695104705284627096694987984014493305483675161440777443
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:1b4190e5-9ccd-4fc3-a9dc-4b7bd4c3788b
```
  - 26.i2c_target_stress_wr.103457732632367739203069987201693986898248605389644505399197286448608693951588
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_wr/latest/run.log
```
  Job ID: smart:a375dbe8-f85a-47d0-a9e6-d5e725b145d7
```
  - ... and 3 more failures.
- ... and 2 more tests.
UVM_ERROR (cip_base_vseq.sv:719) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 8 failures:
- Test i2c_target_stress_all_with_rand_reset has 8 failures.
  - 12.i2c_target_stress_all_with_rand_reset.10484592007825338616946875122352315820861492315322899105994299378149026134264
    Line 354, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7586644811 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7586644811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_stress_all_with_rand_reset.2842465424331750058254165990085780132239249374881943531664079695810463523346
    Line 390, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33128206475 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 33128206475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 7 failures:
- Test i2c_target_stress_all_with_rand_reset has 7 failures.
  - 0.i2c_target_stress_all_with_rand_reset.25528029290466012517768204628877561612368253104760937556848036467647111716689
    Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  17323357 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  17323357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.i2c_target_stress_all_with_rand_reset.43749102595803740809169974570513238145104989012891513755894681413880392178423
    Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3093766711 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 3093766711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 10.i2c_target_stress_all_with_rand_reset.71404717110044080632831197615591965766190965415200505509938713685030472768394
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 780404560 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x56a1fb94) == 0x0
  UVM_INFO @ 780404560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.i2c_target_stress_all_with_rand_reset.48252584076619660996267117573125881748686448560814612385680832894093009578798
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1927735469 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x1bb0e394) == 0x0
  UVM_INFO @ 1927735469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 2.i2c_target_stress_all_with_rand_reset.77835131244800644033314982709425742800739780307484067821598645804764896581875
    Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31272491025 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (62 [0x3e] vs 22 [0x16])
  UVM_INFO @ 31272491025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.i2c_target_stress_all_with_rand_reset.18759292678879214138825806739235394650156137705681690866522475311649097801218
    Line 476, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 80783819098 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (64 [0x40] vs 12 [0xc])
  UVM_INFO @ 80783819098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:56) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 2 failures.
  - 16.i2c_host_stress_all_with_rand_reset.91339377856692879917770371066868779640034373446496517449972939523809310180277
    Line 1847, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7088849545 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 7088849545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.i2c_host_stress_all_with_rand_reset.96851678320739913724842975257168876530148395861988893350999592622625276055347
    Line 516, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120651336 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (4 [0x4] vs 2 [0x2])
  UVM_INFO @ 120651336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test i2c_target_bad_addr has 2 failures.
  - 24.i2c_target_bad_addr.113259672629273505984684838911573936969694752063612423516299328836387287393477
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.i2c_target_bad_addr.115087312206332088821628017906591345672511470028219990383848312149130875724552
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_i' has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 23.i2c_target_stress_all_with_rand_reset.52494536183205951313656692810777515653470514499457341188833410769511515857349
    Line 351, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 7058295453 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 7058295453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```