I2C Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	2.641m	13.120ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	38.014m	100.000ms	8	50	16.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	32.107us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.810s	26.135us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.050s	204.034us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.570s	244.289us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.520s	67.119us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	26.135us	20	20	100.00
		i2c_csr_aliasing	1.570s	244.289us	5	5	100.00
V1		TOTAL			113	155	72.90
V2	host_error_intr	i2c_host_error_intr	2.010s	41.060us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	55.976m	18.968ms	13	50	26.00
V2	host_perf	i2c_host_perf	13.512m	52.276ms	49	50	98.00
V2	host_override	i2c_host_override	0.730s	51.315us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	10.850m	32.623ms	43	50	86.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	4.728m	7.469ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.280s	838.902us	3	50	6.00
		i2c_host_fifo_fmt_empty	27.100s	494.039us	49	50	98.00
		i2c_host_fifo_reset_rx	15.050s	593.280us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	6.157m	16.851ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	1.039m	5.557ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	4.423m	3.236ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.862m	8.958ms	49	50	98.00
V2	target_error_intr	i2c_target_unexp_stop	10.670s	2.884ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	4.210s	3.789ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	54.904m	116.202ms	46	50	92.00
V2	target_perf	i2c_target_perf	5.810s	4.131ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	32.024m	100.000ms	32	50	64.00
		i2c_target_intr_smoke	7.590s	2.009ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.218m	10.057ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.456m	10.097ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	54.052m	58.586ms	45	50	90.00
		i2c_target_stress_rd	32.024m	100.000ms	32	50	64.00
		i2c_target_intr_stress_wr	12.906m	21.840ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	8.860s	7.747ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	57.508m	38.831ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	7.200s	2.011ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.390s	1.589ms	50	50	100.00
V2	alert_test	i2c_alert_test	0.670s	16.985us	50	50	100.00
V2	intr_test	i2c_intr_test	0.760s	10.192us	4	50	8.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.020s	261.262us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.020s	261.262us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	32.107us	5	5	100.00
		i2c_csr_rw	0.810s	26.135us	20	20	100.00
		i2c_csr_aliasing	1.570s	244.289us	5	5	100.00
		i2c_same_csr_outstanding	1.140s	61.327us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	32.107us	5	5	100.00
		i2c_csr_rw	0.810s	26.135us	20	20	100.00
		i2c_csr_aliasing	1.570s	244.289us	5	5	100.00
		i2c_same_csr_outstanding	1.140s	61.327us	20	20	100.00
V2		TOTAL			1270	1442	88.07
V2S	tl_intg_err	i2c_tl_intg_err	2.130s	465.219us	20	20	100.00
		i2c_sec_cm	0.970s	64.129us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.130s	465.219us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.091m	35.008ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.973m	54.270ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1408	1722	81.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	31	31	19	61.29
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.49	98.70	95.33	100.00	93.04	97.32	100.00	91.07

Failure Buckets

UVM_ERROR (i2c_base_vseq.sv:531) [i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '* (* [*] vs * [*]) has 68 failures:

Test i2c_intr_test has 46 failures.

0.i2c_intr_test.50281418076034968605306474017407025187526993858935943899416675397915562194476
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_intr_test/latest/run.log

  UVM_ERROR @  52649329 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (80 [0x50] vs 0 [0x0])
  UVM_INFO @  52649329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_intr_test.43170074605926337132914089142581688912426696458194404621945044186606105549050
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_intr_test/latest/run.log

  UVM_ERROR @  39233584 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (256 [0x100] vs 0 [0x0])
  UVM_INFO @  39233584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 44 more failures.

Test i2c_host_stress_all has 20 failures.

2.i2c_host_stress_all.66780738682289855161998190387500386050945836647484796208383534335624138421626
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @   8800317 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (512 [0x200] vs 0 [0x0])
  UVM_INFO @   8800317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_host_stress_all.44270599743079233217748704415606624205475929401183950989598539330328860954176
Line 1769, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20505109380 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (8720 [0x2210] vs 0 [0x0])
  UVM_INFO @ 20505109380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test i2c_host_stress_all_with_rand_reset has 2 failures.

9.i2c_host_stress_all_with_rand_reset.70903069661788832249582152296054470816290917106155339538500327847118492719237
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 112214393 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (576 [0x240] vs 0 [0x0])
  UVM_INFO @ 112214393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_host_stress_all_with_rand_reset.56961911111813215165875648221407040322849102254684652864384870583193250699542
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  64345788 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (16448 [0x4040] vs 0 [0x0])
  UVM_INFO @  64345788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_base_vseq.sv:531) [i2c_host_fifo_reset_fmt_vseq] Check failed cfg.intr_vif.sample() & mask == '* (* [*] vs * [*]) has 47 failures:
- Test i2c_host_fifo_reset_fmt has 47 failures.
  - 0.i2c_host_fifo_reset_fmt.36343375578894404141783270833112736342515993998460009563889096413134147360976
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest/run.log
```
  UVM_ERROR @  93609221 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_reset_fmt_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  93609221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_host_fifo_reset_fmt.71587365321244537958149621266296580448321252655811249739297836784921367983424
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest/run.log
```
  UVM_ERROR @ 234843727 ps: (i2c_base_vseq.sv:531) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_reset_fmt_vseq] Check failed cfg.intr_vif.sample() & mask == '0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 234843727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 45 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 45 failures:
- Test i2c_host_stress_all has 3 failures.
  - 0.i2c_host_stress_all.64004391763739016838090333300479637575568716851895795027268145357156972400689
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:737e1476-5bb6-4766-96b1-eaa7db9d3c52
```
  - 1.i2c_host_stress_all.87332150190420940984586967753849474007343788993356442885397918555428385471347
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:265b318a-decc-499f-aa4c-e19a583419aa
```
  - ... and 1 more failures.
- Test i2c_target_stress_all has 4 failures.
  - 0.i2c_target_stress_all.77917025016515819574715616860782372698364262079478920470457231145857422080790
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:82be71dd-4d99-4001-9824-021de2a64055
```
  - 9.i2c_target_stress_all.66623494377017474395510074651319267324144007891436781765451822609000776293930
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:7cad6a28-e20c-44a7-baa3-a33e1def3f41
```
  - ... and 2 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 2.i2c_host_stress_all_with_rand_reset.66061182516421348205865311491361932269814927892285630213076134624644583641408
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:82d92b83-97a0-4003-b63d-1e3b7e3f2a88
```
  - 12.i2c_host_stress_all_with_rand_reset.52907272763703223527163227410200243865559706958685100241674135432904140834715
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:46be88ae-62a9-498f-936b-636273860ae8
```
  - ... and 2 more failures.
- Test i2c_target_stress_rd has 13 failures.
  - 5.i2c_target_stress_rd.66994468911991923771942543555590485016416645182325452758632810828197684854062
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_rd/latest/run.log
```
  Job ID: smart:95a385e1-e66a-48cc-ad95-ec7b0638a87e
```
  - 9.i2c_target_stress_rd.79065819280675020305682820173268786323509951834114283767432510182824835785266
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_rd/latest/run.log
```
  Job ID: smart:fdbf5803-69c0-4b37-9bee-7fa8c027e840
```
  - ... and 11 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 5.i2c_target_stress_all_with_rand_reset.49043606914745781167003904317459807098087885240886933648945596131125413494290
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0f270e0f-2882-4dbc-9cf0-024d25afc649
```
- ... and 5 more tests.

UVM_ERROR (cip_base_vseq.sv:788) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:

Test i2c_host_stress_all_with_rand_reset has 28 failures.

0.i2c_host_stress_all_with_rand_reset.115167886827334625442241333980280730539698920599269979690526600905671578244445
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1876033918 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1876033918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.30893534056941327043612875604921394415262476438264398197624641771926431144128
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 215938922 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 215938922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

3.i2c_target_stress_all_with_rand_reset.8522019509926335621531025425048520939595161277139071744076015988582241631860
Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7513867463 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7513867463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_target_stress_all_with_rand_reset.92475119157616331736180341966520392615818928993013719205693059734791524395168
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 170845423 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 170845423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 30 failures:
- Test i2c_target_smoke has 24 failures.
  - 0.i2c_target_smoke.85168556176014756888245618307146783312673055413754675162752680999903494416634
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_smoke.31036958660580077332648558851212774950540862533880710721490170695639718208282
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
- Test i2c_target_stress_rd has 5 failures.
  - 1.i2c_target_stress_rd.31383590713942339376420945798348815497430830114305880941267802047173175453854
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_rd/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_rd.11438182535247225248470321902170441997113309517095784543957721300531789169600
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_rd/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test i2c_host_fifo_fmt_empty has 1 failures.
  - 40.i2c_host_fifo_fmt_empty.919624705418660901793233149789699441572109831262252583489579834616612746856
    Line 1090, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest/run.log
```
  UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:460) [i2c_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRi2c_reg_block.intr_state has 26 failures:

Test i2c_host_stress_all has 11 failures.

3.i2c_host_stress_all.23256584001081557934110809895104599300358471222498420893374367608210719758462
Line 1577, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 8065470820 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (5098 [0x13ea] vs 7147 [0x1beb]) when reading the intr CSRi2c_reg_block.intr_state
  UVM_INFO @ 8065470820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.i2c_host_stress_all.92839462786638819086018874602852593900753665251554441661078684038173172450752
Line 7868, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 122576709166 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (25789 [0x64bd] vs 27837 [0x6cbd]) when reading the intr CSRi2c_reg_block.intr_state
  UVM_INFO @ 122576709166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test i2c_host_stress_all_with_rand_reset has 15 failures.

4.i2c_host_stress_all_with_rand_reset.10679056855596953440936659853862084483291833967753427208891002806617891336067
Line 617, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10927438359 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (22312 [0x5728] vs 24361 [0x5f29]) when reading the intr CSRi2c_reg_block.intr_state
  UVM_INFO @ 10927438359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_host_stress_all_with_rand_reset.18770527792611720102948898666763397025901867872220505704019880941631093314737
Line 2951, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10462980187 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (27908 [0x6d04] vs 27909 [0x6d05]) when reading the intr CSRi2c_reg_block.intr_state
  UVM_INFO @ 10462980187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 15 failures:
- Test i2c_target_stress_all_with_rand_reset has 15 failures.
  - 6.i2c_target_stress_all_with_rand_reset.38097277079651455196041958074210840957501714131945452809370365497448838139988
    Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2176048374 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 10 [0xa])
  UVM_INFO @ 2176048374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_stress_all_with_rand_reset.12265295516560906436389422767695058152469008731250724822645150901065555758949
    Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30672444998 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 30672444998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 11 failures:

Test i2c_host_fifo_watermark has 7 failures.

0.i2c_host_fifo_watermark.114739884390771065828565376051522788355763026038602182814940607125287512043367
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest/run.log

  UVM_ERROR @ 313903404 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 313903404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_fifo_watermark.49942490594310200168078976728408264630394564862413539054664168685114198066146
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest/run.log

  UVM_ERROR @ 402113191 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 402113191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test i2c_host_stress_all has 3 failures.

9.i2c_host_stress_all.12924417233215673581715585844556047953531908061705819675114665848786522860463
Line 2029, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 1932864081 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 1932864081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.i2c_host_stress_all.31742520828728944285453994352106084719970242367581679323746921860062260377757
Line 581, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19693228012 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 19693228012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test i2c_host_stress_all_with_rand_reset has 1 failures.

20.i2c_host_stress_all_with_rand_reset.87003400121861633047600690068440167827261324972693564817793621133557050244889
Line 516, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 459853163 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 459853163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 9 failures:
- Test i2c_target_stress_all_with_rand_reset has 9 failures.
  - 1.i2c_target_stress_all_with_rand_reset.76882381087501585162818962020051783713798634566475898605560460977145077185211
    Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1230542314 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 1230542314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_stress_all_with_rand_reset.62421109522503965445999089014844658975564031975262752961027734787639457798193
    Line 319, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9652976450 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 9652976450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 9 failures:
- Test i2c_target_smoke has 9 failures.
  - 2.i2c_target_smoke.115684817667122456635275310018169165127315612433760316898244164680228065671377
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest/run.log
```
  Job ID: smart:7baa5c27-76e9-4060-8e0a-c7dcfc06d706
```
  - 8.i2c_target_smoke.61810965093086021516305523825910237600531867873761926293208354861314323271948
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_smoke/latest/run.log
```
  Job ID: smart:f9e64ab1-b367-4c54-8f0d-cfbd0b4c5584
```
  - ... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 9 failures:
- Test i2c_target_stress_all_with_rand_reset has 9 failures.
  - 9.i2c_target_stress_all_with_rand_reset.3927619759249402495582919886673350690816901845060584679205054875826246980091
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 662826073 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8b62f194) == 0x0
  UVM_INFO @ 662826073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stress_all_with_rand_reset.109150176699348141727620449542792626140894126030313605850643927278136502603017
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2413882596 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xafa3294) == 0x0
  UVM_INFO @ 2413882596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 0.i2c_target_stress_all_with_rand_reset.26585644750737173600512112739775723932490601298631181803055324004012278476168
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1218029689 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
  UVM_INFO @ 1218029689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all_with_rand_reset.68301996077885996680067816967214404705547789241452614083004690714899020407781
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1189213285 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
  UVM_INFO @ 1189213285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending 'scl_i' has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 16.i2c_target_stress_all_with_rand_reset.34118399308497792894032501210450246698209224014461067986801685203108714474009
    Line 392, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 34959653371 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 34959653371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 20.i2c_target_stress_all_with_rand_reset.17520166170817215124146596483694529533571679734076456136164756218625776958169
    Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 2359600722 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 2359600722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 11.i2c_target_stress_all_with_rand_reset.114765979516170786313800622476678455229703909026930720840264645082118278318502
    Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3761152338 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (108 [0x6c] vs 232 [0xe8])
  UVM_INFO @ 3761152338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 23.i2c_host_mode_toggle.78809141392654911966855742895773634405993619170138739826165399024064804634452
    Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @  57176340 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```