I2C Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.609m	7.265ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	46.020s	9.779ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.780s	21.321us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.800s	363.780us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.040s	655.328us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.200s	143.359us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.760s	35.579us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.800s	363.780us	20	20	100.00
		i2c_csr_aliasing	2.200s	143.359us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.010s	210.684us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	53.986m	139.330ms	47	50	94.00
V2	host_maxperf	i2c_host_perf	28.950m	46.803ms	50	50	100.00
V2	host_override	i2c_host_override	0.750s	21.639us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.069m	4.256ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.580m	17.010ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.220s	261.728us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.790s	988.052us	50	50	100.00
		i2c_host_fifo_reset_rx	9.800s	379.908us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.508m	5.507ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	40.170s	4.954ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.576m	8.240ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	7.910s	1.056ms	4	50	8.00
V2	target_glitch	i2c_target_glitch	12.930s	2.610ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	12.944m	35.314ms	6	50	12.00
V2	target_maxperf	i2c_target_perf	1.090s	407.453us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.294m	5.140ms	50	50	100.00
		i2c_target_intr_smoke	8.660s	12.255ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.410m	10.029ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.460m	10.061ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	29.605m	62.208ms	50	50	100.00
		i2c_target_stress_rd	1.294m	5.140ms	50	50	100.00
		i2c_target_intr_stress_wr	8.316m	21.596ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.340s	1.600ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	54.668m	19.732ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	5.620s	5.254ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.690s	2.329ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	6.069m	4.256ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_tx_stretch_ctrl	target_mode_tx_stretch_ctrl			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.670s	22.527us	50	50	100.00
V2	intr_test	i2c_intr_test	0.710s	76.945us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.560s	178.105us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.560s	178.105us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.780s	21.321us	5	5	100.00
		i2c_csr_rw	0.800s	363.780us	20	20	100.00
		i2c_csr_aliasing	2.200s	143.359us	5	5	100.00
		i2c_same_csr_outstanding	2.330s	778.309us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.780s	21.321us	5	5	100.00
		i2c_csr_rw	0.800s	363.780us	20	20	100.00
		i2c_csr_aliasing	2.200s	143.359us	5	5	100.00
		i2c_same_csr_outstanding	2.330s	778.309us	20	20	100.00
V2		TOTAL			1245	1392	89.44
V2S	tl_intg_err	i2c_tl_intg_err	2.390s	162.395us	20	20	100.00
		i2c_sec_cm	0.930s	94.460us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.390s	162.395us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.784m	64.284ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.493m	15.196ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	29.550s	3.016ms	50	50	100.00
		TOTAL			1475	1722	85.66

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	36	30	25	69.44
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.38	97.15	90.91	97.67	83.58	94.42	98.45	91.47

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 103 failures:
- Test i2c_target_perf has 50 failures.
  - 0.i2c_target_perf.109058739504629430907019008518983183901817793923249218779754704861129397815264
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  24433802 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  24433802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.931465051997303095510516534980148661797564580137432259255554300706735353302
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 107181572 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 107181572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.
- Test i2c_target_stress_all has 28 failures.
  - 0.i2c_target_stress_all.58211161934009093421376202219729491169872763111500534214225488366808184212083
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  61814153 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  61814153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_all.89970284064804865634153162558389272613474895484953930843256390105255695433051
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  38879017 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  38879017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
- Test i2c_target_stress_all_with_rand_reset has 25 failures.
  - 1.i2c_target_stress_all_with_rand_reset.4140383038019004147256192308026633389813942019629850270830732280760829727727
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  82472874 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  82472874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all_with_rand_reset.55657136428286751727926526828364861444019234945067772497989158689652696051858
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  53287596 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  53287596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 59 failures:
- Test i2c_target_unexp_stop has 45 failures.
  - 0.i2c_target_unexp_stop.10423617961185567820806093810443832122259027329123371531853653219656768303384
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 899383398 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 899383398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.65564508815563064144066852543634545159852547360638774886641783185118014173381
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1207248562 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1207248562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 43 more failures.
- Test i2c_target_stress_all has 14 failures.
  - 11.i2c_target_stress_all.42242578777953954721645138365370008082227435114888349475575006453195938713311
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 1744132288 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1744132288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_stress_all.12702597428376882144417085554545562511699655801326917500178660235269755846404
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 4081608040 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4081608040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 54 failures:

Test i2c_host_stress_all_with_rand_reset has 44 failures.

0.i2c_host_stress_all_with_rand_reset.17167615539101581013787939596022949007386162140380360682990292178450911837967
Line 398, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19419482624 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19419482624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.56616392185461880694862498797248271766058434863959222567392680652042581800360
Line 465, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3447790420 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3447790420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 42 more failures.

Test i2c_target_stress_all_with_rand_reset has 10 failures.

5.i2c_target_stress_all_with_rand_reset.103883514300912290163769124408483663479744200219195870371645914184735044849628
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28577295903 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28577295903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_stress_all_with_rand_reset.103611842795764648518018689095808536245967645358880545469192142004526835128381
Line 354, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 76870999999 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 76870999999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test i2c_host_stress_all has 3 failures.
  - 3.i2c_host_stress_all.72556269636002140717001492316531383029170204249060254447978307209180481759403
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:807e59a4-f7e1-4791-ae14-d676365503ad
```
  - 25.i2c_host_stress_all.21404852818015839862409917309928670950309520515800816094680210115410576046207
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:a58a3d6e-22c0-4c5c-8573-e0b814cb9d64
```
  - ... and 1 more failures.
- Test i2c_host_stress_all_with_rand_reset has 6 failures.
  - 8.i2c_host_stress_all_with_rand_reset.12090721514096559659322356323491269782070420568290867289244237267100956253189
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:16eb9e10-8913-43c3-9911-384f405db82b
```
  - 10.i2c_host_stress_all_with_rand_reset.81520350189224550306051608858660635511414752481736893273561833172393936769338
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1edd3e61-bcae-49eb-ac6c-4746e1c8b1fb
```
  - ... and 4 more failures.
- Test i2c_target_stretch has 4 failures.
  - 33.i2c_target_stretch.49198244847550079180046979577733530945719113564149564345541399917710998138545
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stretch/latest/run.log
```
  Job ID: smart:ed7cb1fd-4dd3-4718-9a5c-419fd4ac49e8
```
  - 35.i2c_target_stretch.48784161954192371962252325856947943135515151616596015390142353191288228807432
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stretch/latest/run.log
```
  Job ID: smart:38dad470-1d87-4fbc-82c2-965f02bb9c76
```
  - ... and 2 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 35.i2c_target_stress_all_with_rand_reset.58673424434139369180097152355266978332205430927611060650865378151657323894674
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f40d05c6-666b-4893-922f-ce143267eff7
```
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 6 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 4.i2c_target_stress_all_with_rand_reset.12265381532580443850470026606975712123378592071251424487422431592103667697076
    Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 832103333 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 832103333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stress_all_with_rand_reset.75879870553958881695225678571192560335723709796298083016786608158855386853632
    Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12649827335 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 12649827335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test i2c_target_stress_all has 1 failures.
  - 25.i2c_target_stress_all.33943264421156209528337094763572126569297357631891278252364154305588786472570
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 13778678482 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 13778678482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 0.i2c_target_stress_all_with_rand_reset.39483959973712636551412334998530665099723492654856335560057821460684097908766
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 639270228 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 639270228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 19.i2c_target_stress_all_with_rand_reset.61423008274510427602380369791218389719250472885624873778056321102281365685952
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 406997301 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 406997301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 13.i2c_target_stress_all_with_rand_reset.77688308840470268783877538871837504129753257453700277709547701149080208161007
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10469670797 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xd46a8014) == 0x0
  UVM_INFO @ 10469670797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.i2c_target_stress_all_with_rand_reset.68799876527002097394344857501258193173531818396577744997984030182585561310088
    Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15196056750 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8a0aba14) == 0x0
  UVM_INFO @ 15196056750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 7.i2c_target_stress_all_with_rand_reset.42313234424417592475429183823418698909480587147260722690237132634683868049619
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12733339957 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 12733339957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_unexp_stop has 1 failures.
  - 11.i2c_target_unexp_stop.45800953218503251350859696076085589673879874503208051458223448986519754126866
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 19198739906 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 19198739906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 35.i2c_target_stress_all.109597839014776384569291448231419208761790303099258947642317887132601231178130
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 10936175103 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 10936175103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```