I2C Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.792m	3.965ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	45.180s	22.528ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	73.163us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.820s	89.324us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.040s	1.243ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.170s	115.564us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.410s	58.264us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.820s	89.324us	20	20	100.00
		i2c_csr_aliasing	2.170s	115.564us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	1.960s	298.214us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	39.195m	87.569ms	47	50	94.00
V2	host_maxperf	i2c_host_perf	43.321m	48.861ms	49	50	98.00
V2	host_override	i2c_host_override	0.720s	85.684us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.888m	23.096ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.672m	11.335ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.210s	669.782us	50	50	100.00
		i2c_host_fifo_fmt_empty	30.500s	1.103ms	50	50	100.00
		i2c_host_fifo_reset_rx	10.330s	758.300us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.226m	24.174ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	34.610s	716.239us	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.698m	13.069ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	7.350s	5.326ms	10	50	20.00
V2	target_glitch	i2c_target_glitch	9.350s	1.678ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	10.616m	36.282ms	3	50	6.00
V2	target_maxperf	i2c_target_perf	1.050s	182.713us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.102m	5.859ms	50	50	100.00
		i2c_target_intr_smoke	7.890s	1.589ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.315m	10.027ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.483m	10.043ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	38.720m	64.931ms	50	50	100.00
		i2c_target_stress_rd	1.102m	5.859ms	50	50	100.00
		i2c_target_intr_stress_wr	10.408m	21.358ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.710s	3.509ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	49.303m	17.431ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	6.320s	5.752ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.500s	3.966ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.888m	23.096ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_tx_stretch_ctrl	target_mode_tx_stretch_ctrl			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.700s	16.492us	50	50	100.00
V2	intr_test	i2c_intr_test	0.700s	39.259us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.920s	107.896us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.920s	107.896us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	73.163us	5	5	100.00
		i2c_csr_rw	0.820s	89.324us	20	20	100.00
		i2c_csr_aliasing	2.170s	115.564us	5	5	100.00
		i2c_same_csr_outstanding	1.270s	256.889us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	73.163us	5	5	100.00
		i2c_csr_rw	0.820s	89.324us	20	20	100.00
		i2c_csr_aliasing	2.170s	115.564us	5	5	100.00
		i2c_same_csr_outstanding	1.270s	256.889us	19	20	95.00
V2		TOTAL			1246	1392	89.51
V2S	tl_intg_err	i2c_tl_intg_err	2.550s	516.835us	20	20	100.00
		i2c_sec_cm	0.970s	189.719us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.550s	516.835us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.312m	39.732ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.099m	10.833ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	27.080s	981.609us	50	50	100.00
		TOTAL			1476	1722	85.71

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	36	30	23	63.89
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.40	97.15	90.83	97.67	83.58	94.42	98.45	91.68

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 98 failures:
- Test i2c_target_perf has 49 failures.
  - 0.i2c_target_perf.34822813096489021742792633538489353259272375975335835603459176447627931489581
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  32801034 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  32801034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_perf.5242821737519437926485380414727519974335670297377037958621669282998070187816
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  61881531 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  61881531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 47 more failures.
- Test i2c_target_stress_all_with_rand_reset has 24 failures.
  - 1.i2c_target_stress_all_with_rand_reset.83901961145503836047727979924014784669783564655397289418845660593967545092089
    Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 614616261 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 614616261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all_with_rand_reset.41498824889457787952266772168779980227436743518808019353764956134904123557254
    Line 319, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4951745196 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 4951745196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
- Test i2c_target_stress_all has 25 failures.
  - 3.i2c_target_stress_all.5317701290977035540470573996256826483120664164118452558539897754955966882237
    Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 11416580732 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 11416580732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_stress_all.84341856571963392853630102929990417293609677052769870282913436402492270586093
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 3459742804 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 3459742804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 58 failures:

Test i2c_target_unexp_stop has 40 failures.

0.i2c_target_unexp_stop.9352493943015784219913186722428342307032769261510996909527857153613962838061
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 851282053 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 851282053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_unexp_stop.109064261389109024819013419168707351820919525835718798140166098153885117959743
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 8457113918 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 8457113918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 38 more failures.

Test i2c_target_stress_all has 18 failures.

0.i2c_target_stress_all.18976163229799380112479991240767270915510822175856609774382799283764396149209
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 12888221493 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 12888221493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all.87756258842768912333836279145163832206414404145062065548339055316740557783506
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 37219609397 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 37219609397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 54 failures:

Test i2c_host_stress_all_with_rand_reset has 44 failures.

0.i2c_host_stress_all_with_rand_reset.80723484833863913614509878136188029832962502825645107870477425427978752096124
Line 1079, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2785175266 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2785175266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.26584074991706704496069357871778103567632888729026377798503570515827599928036
Line 2210, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3126898860 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3126898860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 42 more failures.

Test i2c_target_stress_all_with_rand_reset has 10 failures.

2.i2c_target_stress_all_with_rand_reset.1894957489298975217858806341021798384543409441970791915738040079525710048954
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5783350345 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5783350345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.85764738494187837089344154506848736508691624843635144553101947799078697376861
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1689043568 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1689043568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test i2c_host_perf has 1 failures.
  - 1.i2c_host_perf.101126698929075968761216563506990555338185010662200011518451455143988897614288
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_perf/latest/run.log
```
  Job ID: smart:af627fad-169c-4046-84df-54789adfa453
```
- Test i2c_target_stretch has 4 failures.
  - 1.i2c_target_stretch.61660514161854012733463674091038441868269196699807028360257293786695307401831
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
```
  Job ID: smart:f3d077eb-babd-4993-8d84-59336993e17e
```
  - 31.i2c_target_stretch.36495660950501608551074324196784721875508949126759800725668509201559831742680
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stretch/latest/run.log
```
  Job ID: smart:da0a1d03-25d5-48f5-bda3-2765d3eac583
```
  - ... and 2 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 6.i2c_host_stress_all_with_rand_reset.69798354670099101683637175416715032081293362438231373716302476414041215564023
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f22575d7-0537-451b-9a17-1ee347d99be0
```
  - 12.i2c_host_stress_all_with_rand_reset.5088793171939998603527170111558240479439060614000956458564123727277592513895
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:38c49384-1cb6-47d0-98da-25dfe8e58eb7
```
  - ... and 2 more failures.
- Test i2c_host_stress_all has 3 failures.
  - 16.i2c_host_stress_all.25833500517673158449481838886008447706243080783341171464899194888019507762400
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:5f18cc11-f6b1-48c4-9799-e61ec1288fb0
```
  - 27.i2c_host_stress_all.36952539773128415554823418214124578667066847805312771235954436679740581963629
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:8a3b8e87-8d58-4a69-bd5a-885a3e65bf75
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 6 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 0.i2c_target_stress_all_with_rand_reset.20997548333227750273320235186522904747561237736037282435121138470794876712721
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  81606073 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  81606073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_stress_all_with_rand_reset.59474189797346180416336140729380069905887857623678432997800578189779105399437
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  35420095 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  35420095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test i2c_target_perf has 1 failures.
  - 1.i2c_target_perf.3336700525221002885229930109235622390325518563785773572685598509187614585739
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  20676082 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  20676082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 9.i2c_target_stress_all_with_rand_reset.12535709801469946563807503151289989175087576832295840110752145006526097771281
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10922777896 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10922777896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.i2c_target_stress_all_with_rand_reset.54237945703484615800436217799368433392006542757871000334562513055350741930824
    Line 315, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 59795462324 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 59795462324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test i2c_target_stress_all has 1 failures.
  - 23.i2c_target_stress_all.98201861962819247874674946596779784655661157419852908725815784368529098918342
    Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 128873141610 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 128873141610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 11.i2c_target_stress_all_with_rand_reset.15784150298363432556887532943257247780332811740982129468834194940755241602238
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 191783023 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 191783023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 19.i2c_target_stress_all_with_rand_reset.17480423680027613709319182657683973928241775624184838613609959201400988127562
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 693176257 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 693176257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all has 3 failures.
  - 7.i2c_target_stress_all.70846255844382035225227783936887767906210175179431120569779458064732888354268
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 12064820316 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (48 [0x30] vs 47 [0x2f])
  UVM_INFO @ 12064820316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.i2c_target_stress_all.73413382663432674057586075174116582721167697185021207178055016575500532786990
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 8158678850 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 2 [0x2])
  UVM_INFO @ 8158678850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 18.i2c_target_stress_all_with_rand_reset.56869254163826054049682950673190472861368488197954820722073633720742511174096
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10832801753 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xdc381d94) == 0x0
  UVM_INFO @ 10832801753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.i2c_target_stress_all_with_rand_reset.111387863889264835356890748045492208090286415181942446384309042593471061138519
    Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13822784386 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf0fdb494) == 0x0
  UVM_INFO @ 13822784386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_host_stress_all_with_rand_reset.110342055841162798130888659972916198976254086174996630472284691776431815102544
    Line 3281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73019645353 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (27 [0x1b] vs 33 [0x21])
  UVM_INFO @ 73019645353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 9.i2c_same_csr_outstanding.79684157429912079849773477836552558423361890216029032211283431837639212753863
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  61563339 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  61563339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 42.i2c_host_stress_all_with_rand_reset.11850467210480619781707837100468520988249107105457541077901392754573720011721
    Line 7931, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42568718629 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```