I2C Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.552m	1.708ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	49.730s	1.288ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	25.963us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.820s	27.822us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.980s	1.668ms	3	5	60.00
V1	csr_aliasing	i2c_csr_aliasing	2.120s	427.547us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.390s	59.260us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.820s	27.822us	20	20	100.00
		i2c_csr_aliasing	2.120s	427.547us	5	5	100.00
V1		TOTAL			153	155	98.71
V2	host_error_intr	i2c_host_error_intr	2.060s	112.935us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	30.273m	22.358ms	45	50	90.00
V2	host_maxperf	i2c_host_perf	27.508m	49.460ms	49	50	98.00
V2	host_override	i2c_host_override	0.720s	16.214us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.593m	4.392ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.695m	8.856ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.260s	527.836us	50	50	100.00
		i2c_host_fifo_fmt_empty	25.050s	1.867ms	50	50	100.00
		i2c_host_fifo_reset_rx	10.820s	1.233ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.006m	2.560ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	36.170s	7.050ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.883m	2.342ms	48	50	96.00
V2	target_error_intr	i2c_target_unexp_stop	8.670s	2.626ms	12	50	24.00
V2	target_glitch	i2c_target_glitch	10.750s	3.927ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	6.719m	39.442ms	1	50	2.00
V2	target_maxperf	i2c_target_perf	1.030s	161.260us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.291m	7.707ms	50	50	100.00
		i2c_target_intr_smoke	7.980s	1.539ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.379m	10.053ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.557m	10.070ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	56.537m	72.120ms	50	50	100.00
		i2c_target_stress_rd	1.291m	7.707ms	50	50	100.00
		i2c_target_intr_stress_wr	8.979m	23.030ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.590s	1.609ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	55.538m	35.082ms	48	50	96.00
V2	bad_address	i2c_target_bad_addr	6.370s	5.610ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.420s	1.114ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.593m	4.392ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_tx_stretch_ctrl	target_mode_tx_stretch_ctrl			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.680s	20.418us	50	50	100.00
V2	intr_test	i2c_intr_test	0.730s	16.917us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.540s	170.343us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.540s	170.343us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	25.963us	5	5	100.00
		i2c_csr_rw	0.820s	27.822us	20	20	100.00
		i2c_csr_aliasing	2.120s	427.547us	5	5	100.00
		i2c_same_csr_outstanding	1.280s	56.327us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	25.963us	5	5	100.00
		i2c_csr_rw	0.820s	27.822us	20	20	100.00
		i2c_csr_aliasing	2.120s	427.547us	5	5	100.00
		i2c_same_csr_outstanding	1.280s	56.327us	20	20	100.00
V2		TOTAL			1245	1392	89.44
V2S	tl_intg_err	i2c_tl_intg_err	2.550s	693.344us	20	20	100.00
		i2c_sec_cm	0.980s	683.499us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.550s	693.344us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.556m	18.907ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.874m	49.551ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	23.460s	577.819us	50	50	100.00
		TOTAL			1473	1722	85.54

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	6	85.71
V2	36	30	23	63.89
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.34	97.15	90.87	97.67	83.58	94.42	98.45	91.26

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 99 failures:
- Test i2c_target_perf has 50 failures.
  - 0.i2c_target_perf.58341558186598863951566720205348215817456580165824860637152753795165349857541
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  34053964 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  34053964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.10051012683348798634243413017654700014212698623420891581081065096779509336879
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  37532736 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  37532736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.
- Test i2c_target_stress_all_with_rand_reset has 24 failures.
  - 0.i2c_target_stress_all_with_rand_reset.3876300658978187839958153558595885067862309462468784901671525049282418069224
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 149791861 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 149791861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all_with_rand_reset.9370585811787213082233042781389933140502010371046957582735876652414339833174
    Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16867334529 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 16867334529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
- Test i2c_target_stress_all has 25 failures.
  - 1.i2c_target_stress_all.65084857246918568978639556110392718183708807642494770466663362889878007691307
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  19025535 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  19025535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all.107922750996080355500814053541946172812863423963647602097527465473943503237909
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 244837922 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 244837922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 60 failures:

Test i2c_host_stress_all_with_rand_reset has 48 failures.

0.i2c_host_stress_all_with_rand_reset.22763382618861684154546152571201583299114947288821012228802387364931108300789
Line 8518, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26882866747 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26882866747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.86853214887858930577374403234370046966341446968902803022544498820772322500686
Line 4310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35529012817 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35529012817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 46 more failures.

Test i2c_target_stress_all_with_rand_reset has 12 failures.

4.i2c_target_stress_all_with_rand_reset.93485914607950792780749185370024326023775461845157171140564072189643100236888
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2475241910 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2475241910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.i2c_target_stress_all_with_rand_reset.13205454495347836806270142673868290804071378073799684341225831962779292815271
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1648058532 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1648058532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 56 failures:

Test i2c_target_unexp_stop has 37 failures.

0.i2c_target_unexp_stop.68869349642052446354180230584818654791591920787536034924542027355010185438540
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 5322063448 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 5322063448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_unexp_stop.42912301632951443921963939292788932763827511465074767652015909862440259489619
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 728456282 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 728456282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 35 more failures.

Test i2c_target_stress_all has 19 failures.

0.i2c_target_stress_all.16449042994448020903264186821113845710392615171555601397931913781544772139055
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 14568037127 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 14568037127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all.39844418686700934009495187233942098883892587868883926389397653339055709318456
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 11938453767 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 11938453767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test i2c_host_stress_all has 4 failures.
  - 9.i2c_host_stress_all.8595031690521788440790665152350640542989813460918410767804616922400909061552
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:2205ea6c-7782-437c-864f-5df35d8ad418
```
  - 13.i2c_host_stress_all.24396525196146741301472552049951223635214397608455751804891109627361655761772
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:bbda47f0-0483-4c28-be14-bbe923af7ee0
```
  - ... and 2 more failures.
- Test i2c_host_perf has 1 failures.
  - 14.i2c_host_perf.85921016958899911686477975577703124677595379661628007924260680714068520655271
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_perf/latest/run.log
```
  Job ID: smart:b61698a4-2ab5-426f-8cbc-0a12e6f0a657
```
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 20.i2c_host_stress_all_with_rand_reset.82372452239589462069581740398545775925379914285725217481981969712435813268240
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:370a6a5d-fef9-4dac-b22c-5aac4881ffe1
```
- Test i2c_target_stress_all has 1 failures.
  - 23.i2c_target_stress_all.79618812554233850541855435182541137352719319735257468053431927240428834459053
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:cb8ddee2-4a6c-46e3-b8e3-eb0102917fbb
```
- Test i2c_target_stretch has 2 failures.
  - 30.i2c_target_stretch.83260761978398235481861679069102538890470077372073371093615658771170542317166
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stretch/latest/run.log
```
  Job ID: smart:09b7418c-b9b9-4092-a09c-213596126af6
```
  - 40.i2c_target_stretch.68478880203292048129288701336876358511074209583536575202323634557039925178958
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stretch/latest/run.log
```
  Job ID: smart:44cb531a-ea86-46d5-8ec6-67dcdb6ededa
```
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 6 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 2.i2c_target_stress_all_with_rand_reset.2171531771493507958474531103178703398397491653826616024982980444154448037992
    Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11426897095 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 11426897095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_target_stress_all_with_rand_reset.9960126000646272253755224601395319046074453541719744310237035783587744295625
    Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 18241935423 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 18241935423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test i2c_target_unexp_stop has 1 failures.
  - 13.i2c_target_unexp_stop.97603676057565685420360163285189537702794995665642725566022025636142915761930
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 13541202092 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 13541202092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all has 1 failures.
  - 14.i2c_target_stress_all.32763502828051479802365930194689811044272803370968178342181824919948035527159
    Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 153948747457 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 153948747457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 9.i2c_target_stress_all_with_rand_reset.106480516643691428062444366651297417792501423335044152788191346209889142801360
    Line 348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 28333937783 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x4274a94) == 0x0
  UVM_INFO @ 28333937783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.i2c_target_stress_all_with_rand_reset.68653308585693154284306580407663368507226060681549106318456031435181187754337
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11287708254 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x11a4b314) == 0x0
  UVM_INFO @ 11287708254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 1.i2c_target_stress_all_with_rand_reset.86910972926596307774290364348986593106648725718099613586202408293182798836692
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 2697951396 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 2697951396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 13.i2c_target_stress_all_with_rand_reset.85579510718923947695696131431197419244464389176784617554204806650928740543747
    Line 494, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 49550718009 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 49550718009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 2 failures:

Test i2c_csr_bit_bash has 2 failures.

3.i2c_csr_bit_bash.98988470825064159831647644971487537830271841937475749796757815225348271581034
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log

      Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
  UVM_ERROR @ 989730179 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
  UVM_INFO @ 989730179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_csr_bit_bash.1700987123217350187772698575028476124076754988994445831692821670035667339978
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log

      Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
  UVM_ERROR @ 2200461521 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
  UVM_INFO @ 2200461521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 17.i2c_target_stress_all_with_rand_reset.95686618384048054672069868025038343503629100804209330465858014194469784825921
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3785574434 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3785574434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.i2c_target_stress_all_with_rand_reset.53402189551258785738522630237503274194969898207452328986472744743672117159552
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3831930533 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3831930533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 29.i2c_target_stress_all.97329021277666165466650409093515954326826776837274073657212553084156797254780
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 18653154432 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 3 [0x3])
  UVM_INFO @ 18653154432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.i2c_target_stress_all.28170329353016108606165282861832050553872282704529609769097249647898193089436
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 36797882341 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (51 [0x33] vs 50 [0x32])
  UVM_INFO @ 36797882341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 11.i2c_host_stress_all_with_rand_reset.27780107684219596926347699374919490937231212959096354203908303029150780328426
    Line 5949, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6299853419 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (6 [0x6] vs 7 [0x7])
  UVM_INFO @ 6299853419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_o' has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 41.i2c_host_mode_toggle.20517678850040280981931119554001315667210566586824098873921412791764488527022
    Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_mode_toggle/latest/run.log
```
      Offending 'scl_o'
  UVM_ERROR @  62079330 ps: (i2c_controller_fsm.sv:924) [ASSERT FAILED] SclOutputGlitch_A
  UVM_INFO @  62079330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 46.i2c_host_stress_all.69324303665938607677765347612633852318695747919281520848844183296907981778140
    Line 1296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 6088163920 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 6088163920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 46.i2c_host_mode_toggle.87342408132429589660348202398606930709357237523768701808261610361480424450227
    Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @ 310041564 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 48.i2c_target_stress_all.22755067391176877411397681679869811210075538261782730303311873755361094994906
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  27935581 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  27935581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```