349bab6601| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.747m | 10.687ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 57.410s | 1.416ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 75.750us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.780s | 46.030us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.470s | 2.501ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.950s | 103.211us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.350s | 68.265us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.780s | 46.030us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.950s | 103.211us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | host_error_intr | i2c_host_error_intr | 8.420s | 3.519ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 44.197m | 32.709ms | 42 | 50 | 84.00 |
| V2 | host_maxperf | i2c_host_perf | 32.284m | 26.097ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.740s | 153.161us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.593m | 22.388ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.717m | 44.417ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.190s | 206.920us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.080s | 2.384ms | 49 | 50 | 98.00 | ||
| i2c_host_fifo_reset_rx | 13.640s | 237.763us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.852m | 25.370ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.190s | 986.560us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.359m | 10.411ms | 48 | 50 | 96.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 34.430m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.840s | 12.628ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 8.347m | 22.893ms | 3 | 50 | 6.00 |
| V2 | target_maxperf | i2c_target_perf | 1.250s | 127.757us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.171m | 3.063ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.470s | 6.370ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.408m | 10.145ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.464m | 10.081ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 41.888m | 63.859ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.171m | 3.063ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.181m | 26.027ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.280s | 1.755ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 54.588m | 35.728ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.540s | 2.048ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.210s | 1.413ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 6.593m | 22.388ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | target_mode_tx_stretch_ctrl | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 16.006us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.720s | 17.827us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.910s | 170.220us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.910s | 170.220us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 75.750us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 46.030us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.950s | 103.211us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.350s | 241.809us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 75.750us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 46.030us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.950s | 103.211us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.350s | 241.809us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1225 | 1392 | 88.00 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.020s | 135.717us | 19 | 20 | 95.00 |
| i2c_sec_cm | 0.940s | 115.157us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.020s | 135.717us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.904m | 24.185ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 15.801m | 22.970ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 35.190s | 814.011us | 50 | 50 | 100.00 | |
| TOTAL | 1451 | 1722 | 84.26 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 36 | 30 | 20 | 55.56 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.85 | 96.56 | 89.70 | 97.67 | 69.64 | 93.55 | 98.44 | 90.42 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 91 failures:
0.i2c_target_perf.101448517085360751442686716347668652596196669226902220497079041133891647613148
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 420143231 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 420143231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.33780249428358321723402665857954554851899277246790902466025607886512117248613
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 29347514 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 29347514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all.20389290990283738168022666355939573942816649905872745514557899386170188367344
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 23525355278 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 23525355278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.22542260759537422760960950643769273944253327736907590462347989157023602530907
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2292905712 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2292905712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
5.i2c_target_stress_all_with_rand_reset.107828869320393049646750768302466294185445746589575418489697822146927453045126
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1517187972 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 1517187972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.64172192773217723887453147562676120485351861600859188672745074873090078424804
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4999954297 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 4999954297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
0.i2c_host_stress_all_with_rand_reset.114691210369700514505473613857343637460433754835011492172186113975087894734022
Line 1000, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3972352163 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3972352163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.31766954105124039822172377701859290264855061563214648915429766965062275291861
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4198201704 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4198201704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
1.i2c_target_stress_all_with_rand_reset.108057784957673069190138139436521060121184348179093340889763068745602468460404
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 654276368 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 654276368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.99056475314019376411827485617002349970120927964227035709797292444819749248057
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1925466122 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1925466122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 38 failures:
2.i2c_target_unexp_stop.64227500818474600327323665180128491712327520483085521116081131241330921769811
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 78620204 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 49 [0x31])
UVM_INFO @ 78620204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.41576324715400118268443069808571715769459149627793126437872207227735524801705
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 518562451 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 150 [0x96])
UVM_INFO @ 518562451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
4.i2c_target_stress_all.5982003069782174996511775955785862743628626453014857781918864707357575797041
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 63332983 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 221 [0xdd])
UVM_INFO @ 63332983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all.67343821788947290909154673529143639004294759412223126889699385375551050439557
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 36746291380 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 103 [0x67])
UVM_INFO @ 36746291380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
4.i2c_target_stress_all_with_rand_reset.32148914527624788921214797109271013640338357249779479999930598447793602890096
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3626002873 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 70 [0x46])
UVM_INFO @ 3626002873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.76872337406759103347852989250608463733034759225382559785091651393386152941543
Line 461, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 68975574582 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 190 [0xbe])
UVM_INFO @ 68975574582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 33 failures:
0.i2c_target_stress_all_with_rand_reset.32941724123191770378551199116624370586418466912780309776064689501139677701969
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22435356 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 22435356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.12829866904752874765662684696350499874666734837374716502166679422570204880816
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 267439069 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 267439069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
2.i2c_target_stress_all.86708027675125867848263507133188705607956569333171377677034546685668286812727
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2924507091 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2924507091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all.105680372622104153495847389500509688269809235695679710655400335657583614723620
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 328977916 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 328977916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
4.i2c_target_unexp_stop.72843284225393811766079452780452889229514917458115728457040489755237232491824
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 941502160 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 941502160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.91580428008110582401449865450234305274197281154175852508835546179538164479158
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 46213252 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 46213252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
1.i2c_target_stretch.106295047375567704759192299618930565083627398803635984922346516060057637948619
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
Job ID: smart:462e111f-2c2b-4c31-9cb1-6a6a99b6c977
14.i2c_target_stretch.68974244255593464026060038776859628289639400751087579505300820944692373971118
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stretch/latest/run.log
Job ID: smart:a4fbf082-9016-470f-8c9e-d3a61a7dc8e1
... and 2 more failures.
2.i2c_host_stress_all.11208127106981292918868927209932806051561704023016620496759279065821627596862
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:b97141a3-5c0e-41d5-97e3-0248c905e563
21.i2c_host_stress_all.94282285578450411726138013516489820894329486087160803076355692088158183720564
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
Job ID: smart:e8484ea0-6b70-48db-83f2-8614e83f781e
... and 3 more failures.
4.i2c_host_stress_all_with_rand_reset.106044279239580485272588092663704315008645272277703103625724366612032668440319
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8cbd17e4-3acf-4f7f-be4e-45be2ef8df45
7.i2c_host_stress_all_with_rand_reset.17927695125329375851021808077431991322095369686123379073726774701940996562195
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d2818acd-74b3-48ac-8d06-ceec6abd382a
... and 3 more failures.
6.i2c_target_unexp_stop.81151661903159569153968634927355569350601517769442622800669758047965716863495
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Job ID: smart:03a4bc76-269f-4f18-b3c1-871122be6c11
10.i2c_target_unexp_stop.21223336447306618009705799977143844017377278120602595642729430738197616182155
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
Job ID: smart:91af3f5d-bab5-4d11-9c28-07c15e97e111
... and 2 more failures.
38.i2c_host_perf.51091703283604944423245038664211843713311978473537990896682129485273725979353
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_perf/latest/run.log
Job ID: smart:15c12a56-6dc9-4b62-8488-0ac3ca896501
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:
Test i2c_target_unexp_stop has 7 failures.
0.i2c_target_unexp_stop.97819401136477024527032672714236270544159328706817616704188021378068545210664
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_unexp_stop.3484637190496459424326909727909349625827267893217892938836431776663590189274
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test i2c_host_fifo_fmt_empty has 1 failures.
24.i2c_host_fifo_fmt_empty.10951412143126694504144566049185034722273924128504318857193799430760462542195
Line 1202, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest/run.log
UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_perf has 1 failures.
40.i2c_host_perf.60790803013664659193120446876443286963912534997202954270535668308812008622127
Line 388, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 8 failures:
Test i2c_host_perf has 1 failures.
8.i2c_host_perf.81175149619447017192086975996952386265919271348440749196530159230090145554610
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_perf/latest/run.log
UVM_ERROR @ 342012448 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all has 3 failures.
12.i2c_host_stress_all.111872626946336364086913777340485419081481524215266529604921545377799006861578
Line 2517, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7705299993 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
14.i2c_host_stress_all.89759814714679505268830186719800169230818698040587962320221233555116847223232
Line 6452, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15235329114 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 1 more failures.
Test i2c_host_error_intr has 1 failures.
25.i2c_host_error_intr.56655949878040751066927994242233738421636850883912124035851841426829376464276
Line 934, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 354665298 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
Test i2c_host_stress_all_with_rand_reset has 3 failures.
34.i2c_host_stress_all_with_rand_reset.83048049235009970511985701918920166069307134698766243848645189763399313757176
Line 10538, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50194554147 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
35.i2c_host_stress_all_with_rand_reset.76919415434512967531390512583259334287384239568832082916644350787599425813803
Line 1783, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2395446577 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
... and 1 more failures.
UVM_ERROR (i2c_base_vseq.sv:990) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 6 failures:
1.i2c_target_unexp_stop.107388574807645717541336642830869862788553433570312331148588146246221196019046
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2241841895 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2241841895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.85910157134136483714859160782782853958115227974950176104109095074729332784490
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 4022675095 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 4022675095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
20.i2c_target_stress_all.44234966767776606766628955914520229439631234791174866400003446741902250198649
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3593999509 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3593999509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
1.i2c_target_stress_all.23301002784997371931383648736286080308821156006839343731563457319376092609338
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 23354651913 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 11 [0xb])
UVM_INFO @ 23354651913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stress_all.58989737205121070546720561944635213902401449094845186292614208133360269131096
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 9715132871 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 2 [0x2])
UVM_INFO @ 9715132871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
48.i2c_target_unexp_stop.96024540411702644548224835774353294629092667732237695526360212361956651709284
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 159601421 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 2 [0x2])
UVM_INFO @ 159601421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 2 failures:
Test i2c_csr_aliasing has 1 failures.
0.i2c_csr_aliasing.95862873621169047930697084008340074847156823938699353396338959994317816504100
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_aliasing/latest/run.log
UVM_ERROR @ 103211061 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 103211061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_tl_intg_err has 1 failures.
1.i2c_tl_intg_err.105980834994690059228381543021082544465255039890733359248585098108725245945952
Line 346, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 205067345 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 205067345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
3.i2c_csr_bit_bash.49151186243427779520219891325849849339111857715998543123166858472358863188516
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 86975839 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 86975839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_csr_bit_bash.98245509382488671114236435743718406860400324192834102314166512203621409025244
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 76041137 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 76041137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
10.i2c_target_stress_all_with_rand_reset.7598936515339736454628126366121023193815170127825132460404086154940614589407
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13925014683 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xb5be5e14) == 0x0
UVM_INFO @ 13925014683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_stress_all_with_rand_reset.10777553750216625198970939024995504630151770990380042863647444609729361525944
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11298998441 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xac8bd014) == 0x0
UVM_INFO @ 11298998441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
23.i2c_target_stress_all_with_rand_reset.113355773431594697981456136129330231621404674785084146750553624185735733433164
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10153161045 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10153161045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 1 failures.
34.i2c_target_unexp_stop.76324693721556259489667766779756156025701172867911788886624993497781312180405
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 14266697192 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 14266697192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_o' has 2 failures:
27.i2c_host_mode_toggle.23591144841041941363813913596105951983499635940636713532806376276417182335535
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 12536278 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 12536278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.i2c_host_mode_toggle.94699575137722509933160790896891255853685434881003085248027303930403365324296
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 42920301 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 42920301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
40.i2c_host_stress_all_with_rand_reset.4684594559886042974255237717840608114370802364739803018380576851351850537755
Line 9804, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55241776447 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (5 [0x5] vs 3 [0x3])
UVM_INFO @ 55241776447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.i2c_host_stress_all_with_rand_reset.73757100248982669806111674951101541388890510336642769077221680899690268063211
Line 5318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13651154369 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 13651154369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
5.i2c_same_csr_outstanding.69780323752561170891588426147504954422715475287462718754383912336436162612291
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 241809079 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 241809079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
46.i2c_target_stress_all_with_rand_reset.56914080737310964116113695951620745985743317276310835284205398255473530558815
Line 342, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8144682093 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (250 [0xfa] vs 133 [0x85])
UVM_INFO @ 8144682093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---