eb776817a5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.831m | 11.242ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 58.540s | 1.492ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 83.779us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 86.673us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.880s | 1.749ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 14.810s | 6.862ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.260s | 48.024us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 86.673us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 14.810s | 6.862ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 11.790s | 305.836us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 53.899m | 40.069ms | 45 | 50 | 90.00 |
| V2 | host_maxperf | i2c_host_perf | 31.856m | 26.974ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.730s | 27.337us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.769m | 13.552ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.522m | 8.256ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.260s | 138.618us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.670s | 2.502ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.710s | 940.130us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.909m | 2.859ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.340s | 1.861ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.507m | 11.069ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 32.248m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.120s | 3.242ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 36.185m | 100.964ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 1.020s | 250.842us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.261m | 1.861ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.690s | 1.636ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.412m | 10.028ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.504m | 10.038ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 36.537m | 63.224ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.261m | 1.861ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.514m | 17.865ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.540s | 1.634ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 53.311m | 39.180ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.510s | 1.359ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.280s | 602.312us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 7.769m | 13.552ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | target_mode_tx_stretch_ctrl | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.700s | 18.780us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.710s | 51.421us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.960s | 612.445us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.960s | 612.445us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 83.779us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 86.673us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 14.810s | 6.862ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.700s | 936.713us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 83.779us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 86.673us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 14.810s | 6.862ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.700s | 936.713us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1232 | 1392 | 88.51 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.450s | 776.287us | 17 | 20 | 85.00 |
| i2c_sec_cm | 0.990s | 91.527us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.450s | 776.287us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 10.919m | 14.276ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 14.256m | 40.314ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 32.200s | 3.382ms | 50 | 50 | 100.00 | |
| TOTAL | 1459 | 1722 | 84.73 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 36 | 30 | 23 | 63.89 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.79 | 96.50 | 89.66 | 97.67 | 69.05 | 93.48 | 98.44 | 90.74 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 97 failures:
0.i2c_target_perf.7261131838588192161322227069400988920398865657221029161655419362773948139068
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 118556145 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 118556145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.10122882578897616138742963749702169909616040144697062868984087253351248567190
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 250841587 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 250841587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all_with_rand_reset.56862339022154111526399283494596844883426220573658042217551959448781157734163
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 238935823 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 238935823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.103902933001644297100827703460141519932344410292341255601087552642438682604834
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 495796013 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 495796013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
1.i2c_target_stress_all.33592134454833851269376955100953161528245007920032501355339656216095639369066
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 4853121633 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 4853121633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.105800312810269637737537927653537610600980412441607260857236679953802785645012
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 10871334892 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 10871334892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 54 failures:
0.i2c_host_stress_all_with_rand_reset.1795191922526327079581450262213120740376306389506558481041924480080684359081
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 564082849 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 564082849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.11762872809246903365452340092721812753160048544697652336865201464497659405156
Line 791, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2703690834 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2703690834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
2.i2c_target_stress_all_with_rand_reset.99860592516624216157051519775306829480978634050456066133940620001108660736747
Line 317, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9418174402 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9418174402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.95502333762161857587410546651940390387589099203437936971996329364961530108058
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 245160970 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 245160970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 39 failures:
2.i2c_target_unexp_stop.12212698930926205564710519881598335265732193686584580273267885199523672419275
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 105159261 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 105159261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.53859883075097734320456771524785977294002901002967772662183351733792517742668
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 63545987 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 63545987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
3.i2c_target_stress_all.18600872593513535657286028664136510041868350981589024123803364793201050526555
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8097309293 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8097309293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all.89933259624042211859290588771832611052119057019193923920265475722547100529041
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 136262395 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 136262395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
17.i2c_target_stress_all_with_rand_reset.92175237080889883741314684553662064083425125170081307238693468076869091887943
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4407137447 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4407137447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stress_all_with_rand_reset.89409513743221044260257647759176050245225289255264373768944620492881234331470
Line 348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9491462275 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9491462275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
0.i2c_target_stress_all.17334637282568009299528636823523255012185021879998144722421578785266313998908
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 51365476048 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 189 [0xbd])
UVM_INFO @ 51365476048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.34528371574627293329007613497849529242452912056836322083364940253097494922684
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5637783894 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 169 [0xa9])
UVM_INFO @ 5637783894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
1.i2c_target_unexp_stop.14815253200927152866124989571576387785647384210202599960854202889959832704739
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 84506427 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 80 [0x50])
UVM_INFO @ 84506427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.80659999758397996419393649967874303619168204309739888029637655123365147012370
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1770407170 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 189 [0xbd])
UVM_INFO @ 1770407170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
5.i2c_target_stress_all_with_rand_reset.84267749429132485352359837956594276870958942958017575293348572160117239556037
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 175049647 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 7 [0x7])
UVM_INFO @ 175049647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.102886083083059281823586898579764564676637380197673066884757777000964707992939
Line 542, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 117359088772 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 124 [0x7c])
UVM_INFO @ 117359088772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
3.i2c_target_stress_all_with_rand_reset.6247606304963371828575234446042870243982542027632198889376814644605827231888
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:6d02b14d-1a2f-43a3-a0a3-3b9b16db178c
45.i2c_target_stress_all_with_rand_reset.69149592619898545697386107768794170828900742464000714468781322565667852414770
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b347272a-8dd2-48f5-a2f7-0e1dda61a61f
Test i2c_host_stress_all has 4 failures.
4.i2c_host_stress_all.55058702543193097474659718421921612149216595903704654156234137520386502178379
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
Job ID: smart:ca0e88ab-77be-4e0e-b3db-ad9131c70f2c
18.i2c_host_stress_all.10052595307050017439586328203743992421878349210345104952060935903100604321014
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job ID: smart:9d922b91-c287-4e89-b1a9-089f83524ef4
... and 2 more failures.
Test i2c_target_stress_all has 1 failures.
14.i2c_target_stress_all.34639968949996612499203486689088434908707772092624127664851449847778795371612
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
Job ID: smart:4565f1f9-de06-4b33-a463-cab0ab026ff0
Test i2c_host_stress_all_with_rand_reset has 2 failures.
14.i2c_host_stress_all_with_rand_reset.15021136568838226038442787097404054696329040298257440307289923834506028808392
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4de3c322-24f0-4991-b595-2347df4b1044
38.i2c_host_stress_all_with_rand_reset.7958421839614731407825343322610208356207709012607332576701025615268705925846
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ff38543a-317d-4078-baad-1a0dac23e676
Test i2c_target_stretch has 2 failures.
27.i2c_target_stretch.52497320298278728807232962909028966072173302220493926485853167790853055407757
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stretch/latest/run.log
Job ID: smart:a404dbe4-b9c7-4913-bed2-9920c0b5193a
49.i2c_target_stretch.39975811716853063307863982335126784619509261221549970394415349726337269402868
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stretch/latest/run.log
Job ID: smart:096a9e9c-d602-460f-86a5-53d5906f5365
... and 2 more tests.
UVM_ERROR (i2c_base_vseq.sv:990) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 7 failures:
0.i2c_target_unexp_stop.108755613044624334379791756541741774777540760722745316254384058244042508694509
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3342414781 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3342414781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.74342950228180432217191868101407241556132881004002990089087915862379837906607
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2931373792 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2931373792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
6.i2c_target_stress_all.37390216126419183196695808189327936363082367513214603941171862374636434718888
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6623315742 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 6623315742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all.24499846298502105313919600083694724148724255773583316044991954170963626420406
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 879744614 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 879744614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
18.i2c_target_unexp_stop.44978675663031862605609478828208607214042064542935092789786387406438555836423
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_unexp_stop.59699270144512296459250463755505806938182184184612273457419122886384780515230
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
1.i2c_target_stress_all_with_rand_reset.85418041185667542954053751713393317751914626045254618475901931893933107494656
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40313932040 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (12 [0xc] vs 11 [0xb])
UVM_INFO @ 40313932040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
11.i2c_target_stress_all.15003352391288435793629004880163875729461878454991466952826082428570308156455
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3705744190 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 1 [0x1])
UVM_INFO @ 3705744190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 2 failures.
17.i2c_target_unexp_stop.75847305197798162501427337744316874488972394834617288661041961202380331990472
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 219632100 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 4 [0x4])
UVM_INFO @ 219632100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_target_unexp_stop.102392304134242697783110405854891546537050741353167074396267942900115670325539
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 572389990 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 6 [0x6])
UVM_INFO @ 572389990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 2 failures:
10.i2c_tl_intg_err.5364862503304715443545699492900409121627936797922812618964263605920841721528
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 56165084 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 56165084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_tl_intg_err.63136427777577950121425197580708249318183683750473851474986527484099089818818
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 66640763 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 66640763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
11.i2c_host_stress_all_with_rand_reset.78235971551402157242117807259689469086803506264898625423277318525030556276319
Line 528, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 227156763 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 227156763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_host_stress_all_with_rand_reset.99237451631793255469416086012129432720292042114119727434031126803318265368824
Line 7370, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16146400750 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 16146400750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred! has 2 failures:
19.i2c_target_stress_all.38500361217600622207477136403028294172090913532938591686852710188521954518079
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 103961987092 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 103961987092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stress_all.1182846372960893283190489517068464352897155388979336699213021257641687820945
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100963780809 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100963780809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
8.i2c_same_csr_outstanding.93610852913851258842598547330207492428310056290455715444670788420107874063796
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 131834615 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x2207b78 read out mismatch
UVM_INFO @ 131834615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
10.i2c_target_stress_all_with_rand_reset.22851827085299254052042855804151435721843829947134177144345847637134571222373
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1103893863 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1103893863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
18.i2c_tl_intg_err.1685457359686290143033157657309678719558646685688344606704186513996869092846
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 135740602 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 135740602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
30.i2c_target_stress_all_with_rand_reset.25365065114149781580103963282041854006322131048435157210962812561141112888282
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9560728849 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (207 [0xcf] vs 18 [0x12])
UVM_INFO @ 9560728849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
45.i2c_host_stress_all.63180388191097575145312089266272763593043984224914104510704879915456926246690
Line 7561, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 43671922728 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value