I2C Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.921m	4.106ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	1.053m	6.422ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.810s	47.035us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.810s	99.974us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.030s	1.759ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.260s	681.240us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.630s	120.427us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	99.974us	20	20	100.00
		i2c_csr_aliasing	2.260s	681.240us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	13.910s	4.868ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	57.525m	75.196ms	44	50	88.00
V2	host_maxperf	i2c_host_perf	41.061m	28.992ms	48	50	96.00
V2	host_override	i2c_host_override	0.750s	49.340us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	7.534m	76.009ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.519m	36.953ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.270s	170.378us	50	50	100.00
		i2c_host_fifo_fmt_empty	28.260s	1.028ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.750s	217.230us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.954m	5.442ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	47.220s	1.052ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.968m	13.381ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	32.019m	50.000ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	11.560s	2.294ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	38.965m	100.583ms	2	50	4.00
V2	target_maxperf	i2c_target_perf	1.070s	71.365us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.285m	1.898ms	50	50	100.00
		i2c_target_intr_smoke	8.710s	6.376ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.373m	10.122ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.481m	10.034ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	37.263m	65.969ms	50	50	100.00
		i2c_target_stress_rd	1.285m	1.898ms	50	50	100.00
		i2c_target_intr_stress_wr	8.752m	21.906ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.440s	6.280ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	37.161m	34.063ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	5.740s	1.219ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.400s	1.047ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	7.534m	76.009ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_tx_stretch_ctrl	target_mode_tx_stretch_ctrl			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.690s	189.064us	50	50	100.00
V2	intr_test	i2c_intr_test	0.820s	21.188us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.860s	811.875us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.860s	811.875us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.810s	47.035us	5	5	100.00
		i2c_csr_rw	0.810s	99.974us	20	20	100.00
		i2c_csr_aliasing	2.260s	681.240us	5	5	100.00
		i2c_same_csr_outstanding	1.300s	116.225us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.810s	47.035us	5	5	100.00
		i2c_csr_rw	0.810s	99.974us	20	20	100.00
		i2c_csr_aliasing	2.260s	681.240us	5	5	100.00
		i2c_same_csr_outstanding	1.300s	116.225us	20	20	100.00
V2		TOTAL			1233	1392	88.58
V2S	tl_intg_err	i2c_tl_intg_err	2.740s	132.062us	17	20	85.00
		i2c_sec_cm	1.010s	1.186ms	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.740s	132.062us	17	20	85.00
V2S		TOTAL			22	25	88.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.473m	380.037ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.106m	23.061ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	29.410s	4.680ms	50	50	100.00
		TOTAL			1460	1722	84.79

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	36	30	24	66.67
V2S	2	2	1	50.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.90	96.53	89.89	97.67	69.64	93.48	98.44	90.63

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 92 failures:
- Test i2c_target_perf has 49 failures.
  - 0.i2c_target_perf.49149396641752446749662591813200807765597472751114659849194318532831357332301
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  18502642 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  18502642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.114035020785004921576128893036136943972986192091198025558427691335113647700779
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  48377037 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  48377037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 47 more failures.
- Test i2c_target_stress_all_with_rand_reset has 18 failures.
  - 0.i2c_target_stress_all_with_rand_reset.51945255476911452142140563518126098576001179460594005802998115868365029334726
    Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1432962646 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 1432962646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_all_with_rand_reset.34613944472468054748167950720499872910864714352060938583802107289787639007300
    Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24122832780 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 24122832780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
- Test i2c_target_stress_all has 25 failures.
  - 1.i2c_target_stress_all.102390191543246921055608541806568610832886586038253818577261853656739356184446
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 5938441850 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 5938441850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all.11265887146725478483893788010878550580309750465044437476376549963759132856325
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 58727096175 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 58727096175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:

Test i2c_host_stress_all_with_rand_reset has 43 failures.

0.i2c_host_stress_all_with_rand_reset.15295835618461942224883467395522008237565913898903933862326601945431262047366
Line 9982, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20612156473 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20612156473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.6642398584152088634086955287188890296336841068597485932718862442850198451284
Line 348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3804035458 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3804035458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 41 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

4.i2c_target_stress_all_with_rand_reset.90291559289884263285773774671443183874611483747705006295561496318962313140803
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3662239668 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3662239668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.5039780127403784663607527273733184180398349825106935574267250517708009160220
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 498863812 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 498863812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 38 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 0.i2c_target_unexp_stop.79218626201205930718571636225849398403987963544552576922757862467552087306481
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 301119063 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 184 [0xb8])
  UVM_INFO @ 301119063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.90719017203878845023955720334598112014217299020128262216836502262695029830689
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 187077360 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 41 [0x29])
  UVM_INFO @ 187077360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
- Test i2c_target_stress_all_with_rand_reset has 12 failures.
  - 2.i2c_target_stress_all_with_rand_reset.19912453928767458372478933445132927546928848411819262683653481192955301046030
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 428124911 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 165 [0xa5])
  UVM_INFO @ 428124911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_target_stress_all_with_rand_reset.65956987151064661684487214680043685269204200130609408339588661419744706813388
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 815809801 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 56 [0x38])
  UVM_INFO @ 815809801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
- Test i2c_target_stress_all has 9 failures.
  - 5.i2c_target_stress_all.18403390012055847734184303779953544685921871346922403132461715605634263813863
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  50813723 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 221 [0xdd])
  UVM_INFO @  50813723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_stress_all.46164288559107807277974698233470354980426805057643572018019067228049623985142
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  43327456 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 215 [0xd7])
  UVM_INFO @  43327456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 31 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 2.i2c_target_unexp_stop.8045419566632806464194926983706328261577605888091088710140218382570197450056
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 206797894 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 206797894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_unexp_stop.28411751394302830768812429012411700331857659823039246034213106634794956013369
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 449836200 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 449836200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
- Test i2c_target_stress_all has 7 failures.
  - 3.i2c_target_stress_all.64562967287509293049815988204272036093625753392369980970612261746231924366312
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 7137052189 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7137052189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_stress_all.45206571566246237533510986789549792007822374211366659258655685092226909159375
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 1618653470 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1618653470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
- Test i2c_target_stress_all_with_rand_reset has 7 failures.
  - 7.i2c_target_stress_all_with_rand_reset.68981831622860700291068911240030102844435561746960338577163933000082423923772
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  42242388 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  42242388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.i2c_target_stress_all_with_rand_reset.48540205569589738938686588696989756588307017276231953204766269524548050398542
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2280492816 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2280492816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
- Test i2c_target_perf has 1 failures.
  - 19.i2c_target_perf.2565991608884490911408740116681789116017875808853349294767302799908510742506
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  46896947 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  46896947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test i2c_host_stress_all_with_rand_reset has 5 failures.
  - 2.i2c_host_stress_all_with_rand_reset.18507039455497084902824466866491796937264300693619358457893326416226727755642
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b20275ac-1160-4bf2-ae50-07c7e5dceba3
```
  - 19.i2c_host_stress_all_with_rand_reset.98759225860664889818230016809990475259818220976589021372937463975266757849264
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2e8dc340-2e25-4076-b09d-c8925fd18e0d
```
  - ... and 3 more failures.
- Test i2c_host_stress_all has 5 failures.
  - 4.i2c_host_stress_all.74537888247369994295441103968172542883177927285507825529716702237372886607082
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:51e2a80e-10b8-4b22-81d2-155a9ab136e3
```
  - 16.i2c_host_stress_all.79706324732592267226197963928938900681134299650764443476690996006693069328015
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:081a780c-9f2b-4a53-a518-0bb0aaa9aee3
```
  - ... and 3 more failures.
- Test i2c_target_stretch has 3 failures.
  - 8.i2c_target_stretch.82265318281376926177567303397611042322443047019267585090538005854014386223117
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
```
  Job ID: smart:fd53abf6-a5c0-441a-b0d0-c3cb14029931
```
  - 26.i2c_target_stretch.995880717017285287430969686633287128330386396830896210579775596592147074271
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stretch/latest/run.log
```
  Job ID: smart:b5cd4412-5080-4072-9359-5b322ff03f9c
```
  - ... and 1 more failures.
- Test i2c_target_unexp_stop has 6 failures.
  - 10.i2c_target_unexp_stop.77130526701676865889246363280199202741334976908803184941614038052438440326729
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:cf78e770-f1bc-4815-87a7-a28089cf4293
```
  - 19.i2c_target_unexp_stop.11832297287388410970925407273128760992601465136275029176186692018835193034581
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:c605a9d3-4e0b-44b4-88cd-821bd9a35b2c
```
  - ... and 4 more failures.
- Test i2c_host_perf has 2 failures.
  - 11.i2c_host_perf.37234286377954628262736599729503939953646936938273688044027367344644487247914
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_perf/latest/run.log
```
  Job ID: smart:c77891db-f9f4-4877-85f7-7503eb6b90b7
```
  - 29.i2c_host_perf.114283251145232430795019544294260416469980023766913825984075708502757035179508
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_perf/latest/run.log
```
  Job ID: smart:10ee8605-331a-460f-81e6-c546b62ee630
```
- ... and 1 more tests.
UVM_ERROR (i2c_base_vseq.sv:990) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 9 failures:
- Test i2c_target_stress_all has 3 failures.
  - 10.i2c_target_stress_all.113099755807518412312266832349581572128090328820524833455400313160888116058943
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 769622575 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 769622575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.i2c_target_stress_all.41604091952292989761879990935360629161604810883298260022772124641731428626231
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2290885476 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2290885476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_unexp_stop has 6 failures.
  - 11.i2c_target_unexp_stop.58605279372128351073069696707758725262114556534425671715360604599542825532786
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 2872545675 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2872545675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.i2c_target_unexp_stop.99417914205163892527988708713327106746825059687326092951679800542138436292584
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 727843017 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 727843017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
- Test i2c_target_unexp_stop has 3 failures.
  - 3.i2c_target_unexp_stop.48955818299568485401777169287123200832479532463422628603847060795418914861550
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 121592512 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 9 [0x9])
  UVM_INFO @ 121592512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_unexp_stop.50811282777798778710529773422218655090650240324731158216868726269542994217642
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  91180368 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 2 [0x2])
  UVM_INFO @  91180368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 17.i2c_target_stress_all_with_rand_reset.35597393647356752879397775356525368617735410144895335939043633761813559327500
    Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5135731638 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 7 [0x7])
  UVM_INFO @ 5135731638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 25.i2c_target_stress_all_with_rand_reset.84251021341352010732949744558172425497215683851061196016018594860984524006300
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10981992653 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x90b7694) == 0x0
  UVM_INFO @ 10981992653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.i2c_target_stress_all_with_rand_reset.97958900246810232055339686913422655433848818966646524525171552082342035623361
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11169069073 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x76d4b914) == 0x0
  UVM_INFO @ 11169069073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 2 failures:
- Test i2c_tl_intg_err has 2 failures.
  - 2.i2c_tl_intg_err.114938594716599663645426142682664981174790697683632277082671752600362645923271
    Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 204641765 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
  UVM_INFO @ 204641765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.i2c_tl_intg_err.88509844806611086509865965948009006546023022772876541050510137076819886112358
    Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_tl_intg_err/latest/run.log
```
  UVM_ERROR @  65711217 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
  UVM_INFO @  65711217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test i2c_target_unexp_stop has 2 failures.
  - 25.i2c_target_unexp_stop.111045384039090774951670279755918558653711944566512180851300886236687747370708
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.i2c_target_unexp_stop.102453738512643566986971697984837644682199761900640444319645367637880139554649
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 26.i2c_target_stress_all_with_rand_reset.62344723161350153303204005450764441653189048671430917753648395900001107845094
    Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2245230585 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (196 [0xc4] vs 208 [0xd0])
  UVM_INFO @ 2245230585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.i2c_target_stress_all_with_rand_reset.98339689460177228714926461625040273307525346749641042020585635076331329409661
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 683449261 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (19 [0x13] vs 18 [0x12])
  UVM_INFO @ 683449261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 2 failures:
- Test i2c_host_stress_all has 1 failures.
  - 38.i2c_host_stress_all.65507671115198842850665537043977422018562559110718217230985158206553022534615
    Line 2566, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 50661411970 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction WRITE item mismatch!
  --> EXP:
  ------------------------------------------------
  Name              Type          Size  Value
```
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 49.i2c_host_stress_all_with_rand_reset.99631475435736377399074317147956513602232742103604623236268697159481105914440
    Line 6693, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55615083180 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
- Test i2c_tl_intg_err has 1 failures.
  - 3.i2c_tl_intg_err.83610994062823153315877872177345284421767413564294378788617346652602437225468
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_intg_err/latest/run.log
```
  UVM_ERROR @  71922793 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
  UVM_INFO @  71922793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 43.i2c_target_stress_all.98668248512154174474938897461269108468399539669083321084986006421112191421203
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 100583187449 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 100583187449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 46.i2c_host_stress_all_with_rand_reset.64679496093579898628287830197582926950894844007260956918853585498672356041598
    Line 782, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 904690766 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (14 [0xe] vs 3 [0x3])
  UVM_INFO @ 904690766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```