d51405297e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.896m | 15.430ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 51.600s | 19.701ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 43.240us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 19.930us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.520s | 305.501us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.090s | 108.668us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.410s | 70.726us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 19.930us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.090s | 108.668us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 23.810s | 2.211ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 53.264m | 143.025ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 54.371m | 49.600ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.800s | 130.873us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.821m | 5.272ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.155m | 11.986ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.460s | 131.786us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.760s | 592.525us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.190s | 905.582us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.265m | 12.427ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 53.840s | 7.789ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.910s | 422.678us | 18 | 50 | 36.00 |
| V2 | target_glitch | i2c_target_glitch | 10.940s | 8.303ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 58.428m | 56.429ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 8.200s | 2.028ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.136m | 1.421ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.900s | 3.199ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.120s | 329.122us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.940s | 497.756us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 47.367m | 61.439ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.136m | 1.421ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.623m | 22.789ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.390s | 6.390ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.516m | 3.814ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.120s | 1.434ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 35.280s | 10.120ms | 21 | 50 | 42.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 4.110s | 820.503us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.750s | 161.266us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 54.371m | 49.600ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 8.588m | 24.671ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 53.840s | 7.789ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 15.300s | 1.244ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.310s | 638.772us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.030s | 4.239ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.740s | 178.114us | 31 | 50 | 62.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.730s | 2.975ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.640s | 553.173us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 28.017us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 17.302us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.900s | 300.736us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.900s | 300.736us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 43.240us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 19.930us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.090s | 108.668us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.200s | 239.687us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 43.240us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 19.930us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.090s | 108.668us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.200s | 239.687us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1671 | 1792 | 93.25 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.500s | 144.371us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.010s | 60.047us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.500s | 144.371us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 6.203m | 21.015ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.750s | 370.339us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 3.147m | 9.012ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1851 | 2042 | 90.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.25 | 97.27 | 89.50 | 97.22 | 72.02 | 94.33 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 33 failures:
1.i2c_host_stress_all.112930277839723700960734363319539363055593247051316872624439650609502399402702
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 47008873083 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12914169
3.i2c_host_stress_all.9205134062456786557573042169904285404200875140649224541768628035862986295294
Line 341, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 143024836044 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22538609
... and 21 more failures.
10.i2c_host_mode_toggle.104662641493832045256409974028631601924101469863452081872568415679909526541445
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 244154673 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @41326
11.i2c_host_mode_toggle.53441630579461564587366590925542039936520563482886688844552707333498405614088
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 303815465 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8694
... and 8 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 29 failures:
0.i2c_target_hrst.6728970948538462567368006410564093480204200696967700236597201722289358968998
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10115991667 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10115991667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.13185434872944621012959042966536857088494235462239507764872053983649092569261
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10320432717 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10320432717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 25 failures:
0.i2c_target_unexp_stop.86741071447827099722607195971326201423705576319438174808985509627862871772449
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 370339036 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 370339036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.52694300315355142080461960785411005489658726502951061997950546924581285387251
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 957398736 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 957398736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 19 failures:
2.i2c_host_mode_toggle.69561224457483669452837620998734621064990239139866968914711746320813608969592
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 51436114 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.13978034188465017668506255667683472727794204150024540165331894158357973035162
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 136634459 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 17 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
3.i2c_target_nack_txstretch.64158395419225133905237774525584478451140859102816440879280730649043903861157
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 521066594 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 521066594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.52218378940226677237885366647406701913874656894495306711950592084921971806488
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 242563820 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 242563820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 19 failures:
5.i2c_target_unexp_stop.44409070057491336694557383846576358491217077839443600681352979268732224604025
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 172336611 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 135 [0x87])
UVM_INFO @ 172336611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_unexp_stop.41192416591288460942140206915137607744688953166637297353246383366427392266442
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 148750520 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 252 [0xfc])
UVM_INFO @ 148750520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.43763518750144980703800673627677058022170211929197382402378943940957478957172
Line 320, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5243787278 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5243787278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.83569616424439399740731205153084656036131784440536151883715983494145373919234
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3732112635 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3732112635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_stress_all_with_rand_reset.66254900020113561371079703104874297490512439336953538366718928208659700502503
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 106889961 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106889961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.99522105872781032831673200875761911977403068480683412149844561250338912081125
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1610499793 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1610499793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
Test i2c_host_stress_all has 10 failures.
0.i2c_host_stress_all.44905790158047743256832533691218160595518458198781277487126743438860879606959
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:051c56f3-0b74-4888-a305-d116d6d428ed
2.i2c_host_stress_all.59821928297168660044602619639156234451820693075979410583094841615080452420355
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:8d1f07eb-c693-40ad-a5dc-5724f3e6aaf1
... and 8 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
1.i2c_host_stress_all_with_rand_reset.53697729917757199476721997946006897528826375565190983646919036319769760735772
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:fc53fefa-f948-4ed5-afaf-2c93a2d11c78
Test i2c_target_stress_all_with_rand_reset has 1 failures.
9.i2c_target_stress_all_with_rand_reset.36145512161674471986032853091887612560194288031072915209236203078671147785748
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f56c9246-dec6-402e-a5c5-e97ff395a0a5
Test i2c_host_perf has 2 failures.
13.i2c_host_perf.765666927036903299040023279673130353000223810109635654484212622849256005030
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_perf/latest/run.log
Job ID: smart:b0666d3c-2904-4344-bf22-5fdf333c98a9
43.i2c_host_perf.89842732501980543394667178004729310221352885836789992596634779897857585855855
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_perf/latest/run.log
Job ID: smart:56912c84-1bc4-49c0-b876-4391f4a5ec08
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
4.i2c_target_unexp_stop.41753822512718131350257172184766050356192887544482274176059464207158839065920
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 255214872 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 255214872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.53386437642034119194874384627919082960306237496218284327131825913860948009019
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 291742974 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 291742974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*) == * has 3 failures:
13.i2c_host_mode_toggle.82157635662042033096109639397295279319155762078713133424341572394998196403040
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 249007792 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x8fd02214) == 0x1
UVM_INFO @ 249007792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_host_mode_toggle.4096100495539573777513593230517882516990457964997575054509882018024351555770
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 187826393 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x50215014) == 0x1
UVM_INFO @ 187826393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
1.i2c_same_csr_outstanding.59187847886250557688501848750824896840090326019027110131672624845789583915128
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 37050583 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 37050583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_same_csr_outstanding.111336851598145741291574168056218269902822289973974875413014926393551726662665
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 21389418 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 21389418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 2 failures:
26.i2c_target_stretch.97413753821079624466475160601298201975735136679545521816367327107768497736003
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10024405106 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10024405106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_stretch.104987382826753593828110109785245124075768437955568977856691709991349973558912
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002717163 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002717163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
0.i2c_target_stress_all_with_rand_reset.101345449283051699777952678202960842886299696033067709891291921635295835842309
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1186786989 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 1186786989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
31.i2c_target_tx_stretch_ctrl.21597477409836025878087347890809363308825951241929049916481433561050485525576
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
36.i2c_target_stress_all.56372859748039954416089998246802935124415108652106912216887198050109746947336
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 81011990813 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 81011990813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---