c04cc5d074| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.051m | 4.615ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.430s | 1.186ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.850s | 25.455us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 90.176us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 2.840s | 705.080us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.330s | 66.453us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.780s | 124.536us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 90.176us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.330s | 66.453us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 45.075m | 600.000ms | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.250m | 88.215ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 23.903m | 27.769ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.770s | 88.090us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.761m | 21.282ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.210m | 51.252ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.370s | 170.604us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.850s | 2.528ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.770s | 905.302us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.984m | 3.472ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.670s | 3.569ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.080s | 904.242us | 13 | 50 | 26.00 |
| V2 | target_glitch | i2c_target_glitch | 11.890s | 2.302ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 40.907m | 61.132ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 7.390s | 2.380ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.198m | 3.285ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.660s | 8.867ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.890s | 707.336us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.800s | 789.758us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 39.047m | 59.703ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.198m | 3.285ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 16.677m | 27.657ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.320s | 1.527ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.829m | 4.132ms | 42 | 50 | 84.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.000s | 1.384ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 46.500s | 10.013ms | 17 | 50 | 34.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.470s | 661.087us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.740s | 167.197us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 23.903m | 27.769ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 9.311m | 23.254ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.670s | 3.569ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 7.500s | 506.587us | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.320s | 1.269ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.990s | 593.196us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.720s | 177.268us | 31 | 50 | 62.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 33.360s | 792.198us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.780s | 563.745us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.720s | 18.561us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 34.794us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.380s | 362.926us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.380s | 362.926us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.850s | 25.455us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 90.176us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 66.453us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 62.709us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.850s | 25.455us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 90.176us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 66.453us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 62.709us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1655 | 1792 | 92.35 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.350s | 144.796us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 151.491us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.350s | 144.796us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 10.920m | 29.399ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.870s | 339.699us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.737m | 316.697ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1835 | 2042 | 89.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.25 | 97.21 | 89.50 | 97.22 | 72.02 | 94.26 | 98.44 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:
0.i2c_host_stress_all.75329044560126185287320886157826111441966212256912412120147099352722443446626
Line 390, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 64207514788 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17379399
2.i2c_host_stress_all.112790738320313118906121403228999454587553454723847199634789883667947042804644
Line 347, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 51227426081 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4241001
... and 20 more failures.
0.i2c_host_mode_toggle.57092408843970006446326669741838834479107996189167592582570860964958301397748
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 247316346 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21126
1.i2c_host_mode_toggle.94226571253977167948619270075992008491074791777739548160334642846204304586392
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 505489125 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @31020
... and 14 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 33 failures:
0.i2c_target_hrst.107443081386256612929182212929316214451915006102151898053994477973121765041779
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10486571445 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10486571445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.9926211778638879641259818097831717104284339456629528779622344044097608441777
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10191739529 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10191739529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
0.i2c_target_unexp_stop.74428996390622636384176096510611864062324824284298245453556631609880418191416
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 142984247 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 184 [0xb8])
UVM_INFO @ 142984247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.44652400847559728071290915177817445530919993669588078925288838704292042417014
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 283565995 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 105 [0x69])
UVM_INFO @ 283565995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
3.i2c_target_stress_all_with_rand_reset.81459566125145283733872621129732197520149499761597451746878018392725213326361
Line 637, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21054225081 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 99 [0x63])
UVM_INFO @ 21054225081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
1.i2c_target_nack_txstretch.114890134792879113889296233640903287577587358748792519112412106055134417082010
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 135880477 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 135880477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.2453652396980467131407962120530107059985053695052801988489565991328006526635
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1220534936 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1220534936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 19 failures:
2.i2c_host_mode_toggle.98879965821283208373229539923931616498831738136004808740573778319570372483761
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 36241528 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
6.i2c_host_mode_toggle.86764947347664028358582790509760667081994391542307535317432599702400771615594
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 23357348 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.70235888001021176874541176005804866695691504929961348992379916092710977164466
Line 391, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15616547534 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15616547534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.15307152082484534543240823024956098866785096178928413210296698516546926552803
Line 342, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8482220043 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8482220043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
2.i2c_target_stress_all_with_rand_reset.113605754237519746543408118338612932967493263477931288773509901558167153343307
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12482262331 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12482262331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.92067770083957436537498924287391137382524951604604712971191377564728554423833
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2362124975 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2362124975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
2.i2c_target_unexp_stop.4691484272255934573539162409452687447349820115905671779237626218325751857396
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 298909897 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 298909897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.58311190179566551859826942148821980749202086504240721552717791548875245853954
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 186619145 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 186619145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 8 failures:
1.i2c_host_stress_all.21092846003607473460670672779720948290339989316852208905085968257205349301382
Line 306, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 40615544188 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5571245
14.i2c_host_stress_all.93871056429814848938832590295276458579569317018755885059555883433004661036352
Line 371, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 74986092404 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @20922249
... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 8 failures:
3.i2c_target_stretch.52693715141282511439923269290449798044235202750323394486392375292239426477506
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10007346879 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10007346879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stretch.3196986307072997284883345499522888314630482626722778867870238468789823684769
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004697708 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004697708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:
6.i2c_target_unexp_stop.90688263798079772957887070011367413605627388211593891280919887779858152685278
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 880032707 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 880032707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_unexp_stop.103478899863565381474350884141439340114613321759458699277879747618757019457823
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 149688690 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 149688690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
0.i2c_target_stress_all_with_rand_reset.103180946857232021633389581913672823206718458121465896303692062636195434372431
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:210d55f4-9895-4dc7-a99f-4190ba938518
1.i2c_target_stress_all_with_rand_reset.114845549679332174134811286028230422243618912766156768883478725205830649588072
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3e88a6f6-9be4-4119-885f-3f3cc22c6382
Test i2c_host_stress_all_with_rand_reset has 1 failures.
3.i2c_host_stress_all_with_rand_reset.114048816010822713165174046084395887548578327249384481937721406711797249155587
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:60e675e7-09b4-41d4-85c8-2923588a4e7d
Test i2c_host_stress_all has 4 failures.
26.i2c_host_stress_all.29759637412801449877015579071206189886910129077555610412691686822735383711548
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
Job ID: smart:916c6ca1-8720-4367-80b7-a568565306c5
27.i2c_host_stress_all.80188760752183489852653061958356076021973246728715530331942867406077106503717
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
Job ID: smart:e5b6447b-7aea-4b89-ae4c-08db1266f921
... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
2.i2c_target_tx_stretch_ctrl.41439670942944270193628002287351532794619802524176254305365619210020950180363
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
26.i2c_target_tx_stretch_ctrl.104074859421525915475042317323800450445021527778855219955069662577371387543117
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
43.i2c_target_fifo_watermarks_tx.24912851937006427841697338761102437097382806238590240240380931245983737995425
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
10.i2c_host_error_intr.97380669393618211266399269387459538313821364210803739546816282149406640465430
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_error_intr/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*) == * has 1 failures:
18.i2c_host_mode_toggle.25610293291352333334993018452656340464226119569461306050425749724845599442123
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 146771705 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xd4817a94) == 0x1
UVM_INFO @ 146771705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
18.i2c_same_csr_outstanding.76492569934397134195436862342419081598408940165257596041490467716846681893114
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 24591734 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 24591734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
25.i2c_host_mode_toggle.26897412156076634987183846139019658343641531900504372896375306735205927450444
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
26.i2c_host_error_intr.43064811819872580334605665880061728585885187045960096044433933878755681563532
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 64712411 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
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