a04e34f557| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.799m | 8.947ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 39.490s | 6.065ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 44.490us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 27.926us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.630s | 449.662us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.970s | 99.283us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.780s | 167.418us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 27.926us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.970s | 99.283us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 33.452m | 600.000ms | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.864m | 110.573ms | 20 | 50 | 40.00 |
| V2 | host_maxperf | i2c_host_perf | 12.136m | 18.269ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.750s | 27.807us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.002m | 5.386ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.374m | 10.595ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.430s | 132.068us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 40.140s | 736.581us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.900s | 551.386us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.277m | 3.248ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 40.400s | 3.763ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.770s | 217.025us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 12.120s | 9.520ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 53.581m | 56.163ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 8.450s | 5.074ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.480m | 9.536ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.420s | 1.244ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.820s | 284.946us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.120s | 311.626us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 59.128m | 66.559ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.480m | 9.536ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 15.505m | 27.388ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.820s | 3.130ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.195m | 6.050ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.760s | 1.685ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 42.810s | 10.156ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.490s | 2.797ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.760s | 203.070us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 12.136m | 18.269ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 27.883m | 24.207ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 40.400s | 3.763ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 17.750s | 1.523ms | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.410s | 621.802us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.130s | 1.085ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.760s | 733.369us | 30 | 50 | 60.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 20.130s | 2.611ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.710s | 2.028ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.730s | 57.647us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 21.252us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.750s | 276.184us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.750s | 276.184us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 44.490us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 27.926us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.970s | 99.283us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 226.996us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 44.490us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 27.926us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.970s | 99.283us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 226.996us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1667 | 1792 | 93.02 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.280s | 130.135us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.950s | 75.335us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.280s | 130.135us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.583m | 22.192ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.950s | 463.236us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.400m | 220.111ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1847 | 2042 | 90.45 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 27 | 55.10 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.38 | 97.30 | 89.65 | 97.22 | 72.62 | 94.40 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:
1.i2c_host_stress_all.80944737519281367834053656589608049923797541638175545628158950599882291454572
Line 320, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 188180327218 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13058615
3.i2c_host_stress_all.84261648075715943342963979110562238435382869817161149823152281242173394476344
Line 488, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 23767302858 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13070791
... and 19 more failures.
5.i2c_host_mode_toggle.109337834945928693801224252960609889322636768967637426220982148875481920791586
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 157982955 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9610
7.i2c_host_mode_toggle.10060878016738354439839541072510340570946643698755639329441702745908895831215
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 98664479 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @52030
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
2.i2c_target_unexp_stop.20034136524020982103664481184367084449772998110396388041625579486637849105503
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 96350523 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 69 [0x45])
UVM_INFO @ 96350523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.9298741060341887404660012490288854714332266238946488641249935934678324700394
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 463235936 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 155 [0x9b])
UVM_INFO @ 463235936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
5.i2c_target_stress_all_with_rand_reset.7180022486221262506660594111290093114567383912577528916460941689582179965084
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 802968997 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 51 [0x33])
UVM_INFO @ 802968997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.90781886808388538415528208175817894949914931323214164223599226810135602569751
Line 346, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8004649395 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 228 [0xe4])
UVM_INFO @ 8004649395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
0.i2c_target_hrst.37487096885615233482996409732090136053746360789985944918802999038848131650194
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10110032523 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10110032523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.71623886709624712781433171564676671129273850897542255619773513620103189265708
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10429086150 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10429086150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
3.i2c_target_nack_txstretch.101302003269786728789338044782352243517456243946309327493941501933263547888499
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 783359200 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 783359200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.87065706603235384660281106424498972424018630914590059513053900084460446325328
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 139730671 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 139730671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
0.i2c_target_unexp_stop.64740999482702212910509384856395691171347841148164960849804592446550721671038
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 13120550 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13120550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.112747151370148776777723945245542031313063009220511001126453456634270232135780
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 201458700 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 201458700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.52031618955682291105998776883554348322021427113182853863562384274215228403040
Line 558, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 241098973630 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 241098973630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.4183639595555284073412964922685392941008036958607366539602371357688168684559
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2243012982 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2243012982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_stress_all_with_rand_reset.72574628523922527597265633012405446748155408693098336279365247685834148875234
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 671798796 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 671798796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.28387178019125713268870252790617324693692475925111453370738516926317799542780
Line 422, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71093739504 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 71093739504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:
2.i2c_host_mode_toggle.73220520489442330452885425550631115129735785618328172082006385384215973890388
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 228434887 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.110636686427599341433622643341368865133768426367621443372063024465535869604179
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 59625857 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 10 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
Test i2c_host_perf has 2 failures.
2.i2c_host_perf.60899295084841023600970535911808778935738733476881938722652891265944353642997
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
Job ID: smart:b7957317-8add-44c3-80c8-900d747dfee7
45.i2c_host_perf.4150559115982173066292316258751577624370643019993120330547927262128609411564
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_perf/latest/run.log
Job ID: smart:19a43536-40b1-49ec-8e48-4b2b4022174a
Test i2c_target_stress_all_with_rand_reset has 1 failures.
4.i2c_target_stress_all_with_rand_reset.16020785676290968145301580533423492272117009826802031969896670984739888275896
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d02157d6-c6aa-43c4-ba1a-3140777a0f97
Test i2c_host_stress_all_with_rand_reset has 1 failures.
7.i2c_host_stress_all_with_rand_reset.115514105510093161213338996284186449390985899345115798236099681703447159893820
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e596f44d-f18e-4764-a224-9411d110f061
Test i2c_host_stress_all has 3 failures.
11.i2c_host_stress_all.1168910479547831715365628956122039280966863937852780091652971703829698729798
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
Job ID: smart:2bbce859-50c1-4715-8fdb-218b4bd464f5
31.i2c_host_stress_all.29713491442460303964678146221254001098499151543913485358397111288219077618951
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
Job ID: smart:d466671f-fb4f-444e-b432-e95ebb6ef429
... and 1 more failures.
Test i2c_host_error_intr has 1 failures.
34.i2c_host_error_intr.20232593281209257926002475922350699751410069358139378944468446004955864770696
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_error_intr/latest/run.log
Job ID: smart:55d69df0-6316-40bd-9311-695a7554f15f
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
2.i2c_host_stress_all.24132222985117459441702200075427321188238939677268197190180352898505523844205
Line 300, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 78405990288 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1016393
14.i2c_host_stress_all.51875236777996437157237181885719579114263056725083663518207500514644448111298
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 41469487054 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13132711
... and 4 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
3.i2c_target_unexp_stop.110576176298629276885245753560137214648068005457106376807781178886784520650789
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 421847909 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 421847909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_unexp_stop.23734602180971934623713705540175312827542270913553937569000457059740128421929
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 244762386 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 244762386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
6.i2c_target_stretch.88968527464818523283403774950445110198817193336222555902977477655249386038087
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10003987162 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10003987162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stretch.98307454530411917704447112702562458936767986977632146400378018768944939763159
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10023399510 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10023399510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
1.i2c_target_tx_stretch_ctrl.48497457213370198519607337594424262146054688152714619826180582996263765858774
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
13.i2c_target_tx_stretch_ctrl.13883712880490197263806257808890973339038674746239086854693205792867174954923
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
12.i2c_target_fifo_watermarks_tx.21740854601170840934257824244332803970716260415912140852203243969409531844348
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*) == * has 4 failures:
24.i2c_host_mode_toggle.105592826587010685068413910086858249612835560545371846404005611811604435930122
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 94136634 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4e690494) == 0x1
UVM_INFO @ 94136634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.i2c_host_mode_toggle.42230030757642009975326186671618968931223720625959198217478899880708016178200
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 18321768 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x79906514) == 0x1
UVM_INFO @ 18321768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_bad_addr has 1 failures.
11.i2c_target_bad_addr.51929113965840383285034831696920388553753442473780963330792698740096276791827
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_error_intr has 1 failures.
48.i2c_host_error_intr.78941132590244222488394435595131744098942893952271904858112148980737306023876
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_host_error_intr/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:749) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
0.i2c_target_stress_all_with_rand_reset.103437402601283004228411231345164203589893968721682859795089850563767968098205
Line 606, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 127275564196 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 127275564196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
14.i2c_same_csr_outstanding.115053555831925634458179243079297997906192777722940419600625199638753027057054
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 13072997 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 13072997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---