aad711e1bc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.133m | 2.570ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 45.840s | 3.062ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 71.822us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 26.279us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.010s | 541.667us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.960s | 411.660us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.520s | 104.386us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 26.279us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.960s | 411.660us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 36.759m | 600.000ms | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.265m | 29.530ms | 21 | 50 | 42.00 |
| V2 | host_maxperf | i2c_host_perf | 48.719m | 49.144ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.740s | 45.615us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.788m | 5.701ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.333m | 19.696ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.380s | 168.403us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.300s | 1.123ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.780s | 425.857us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.210m | 4.015ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.550s | 5.033ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.380s | 762.242us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 11.230s | 2.456ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.363m | 57.900ms | 47 | 50 | 94.00 |
| V2 | target_maxperf | i2c_target_perf | 8.240s | 3.001ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.257m | 1.896ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.940s | 1.470ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.890s | 282.723us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.830s | 259.920us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 53.289m | 64.653ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.257m | 1.896ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.042m | 16.709ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.090s | 11.142ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 7.353m | 7.224ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.580s | 5.431ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 32.980s | 10.139ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.690s | 697.167us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.770s | 588.801us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 48.719m | 49.144ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 14.927m | 24.277ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.550s | 5.033ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 14.620s | 1.284ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.330s | 3.250ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.040s | 770.028us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.760s | 142.233us | 31 | 50 | 62.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 29.210s | 944.366us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.830s | 600.686us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.750s | 39.327us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 17.123us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.620s | 55.018us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.620s | 55.018us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 71.822us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 26.279us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.960s | 411.660us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 65.005us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 71.822us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 26.279us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.960s | 411.660us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 65.005us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1670 | 1792 | 93.19 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.350s | 517.049us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.040s | 119.805us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.350s | 517.049us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 10.508m | 33.580ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.150s | 1.306ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 8.454m | 111.059ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1850 | 2042 | 90.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.29 | 97.21 | 89.46 | 97.22 | 72.02 | 94.26 | 98.44 | 90.42 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 42 failures:
2.i2c_host_stress_all.85963545362525180781766516013002867375748748799707037046884660989040232824211
Line 371, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 41104774169 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3901365
3.i2c_host_stress_all.99305781397602044539441288582506276556998290652349015014865705442238715022281
Line 380, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18619524989 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4167827
... and 20 more failures.
5.i2c_host_mode_toggle.103702519016701876370708826886153276979684396494304730792046997750298056379857
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 282430432 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @111820
8.i2c_host_mode_toggle.77232190801314285017836615472209138133052477488947398740567901769411972913096
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 111864671 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @90658
... and 18 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
0.i2c_target_hrst.53453988773195561263528579893441207318396606971109224250099964414981283603383
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10004565279 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10004565279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.35420416393092682661804520836479547572396625558970332891657212846159922737216
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10176522183 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10176522183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
0.i2c_target_stress_all_with_rand_reset.106181578221898345446229888659092934437600932041255081463634552962879829976221
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 156344903 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 45 [0x2d])
UVM_INFO @ 156344903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.54655009791490694123791379342920442582480623540724335616159409432315748530653
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 510086385 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 173 [0xad])
UVM_INFO @ 510086385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 26 failures.
1.i2c_target_unexp_stop.31569047068407870532452875131518673732645188286747751900478786915711139658598
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 54141832 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 246 [0xf6])
UVM_INFO @ 54141832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.17155186136866077614826360000579736714112662197086588346501579378958608772463
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 253901689 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 168 [0xa8])
UVM_INFO @ 253901689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
0.i2c_target_nack_txstretch.7013438857200781117614214373420284005670048577515356744811325690369871576305
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 138267413 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 138267413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.16639042646579166534844936987291204457119381582893858814514609053810951453659
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 734649615 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 734649615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
3.i2c_target_unexp_stop.9903543576914379689468031030017686065164380901668273473214555275612654003487
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 331504241 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 331504241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.109144296430980914221309644506918310373637756323801919002938789665516368725708
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 46005979 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 46005979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.90730707474911428343007221075950704315249620090544921855221759208158747324723
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18055897460 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18055897460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.86001091710932034780554253786262313546686688866660412620519556459697472751829
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2607793411 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2607793411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_stress_all_with_rand_reset.28603996645412807945544188141284468620689165175855196499160901119258023930563
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 797957720 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 797957720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.89088191298185528961964209093106943626218331493306127482629532947704014568703
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1498038206 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1498038206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:
3.i2c_host_mode_toggle.95369422765512504759295348722503965071076156216109367159829320740933082890544
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 181052014 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
7.i2c_host_mode_toggle.60590651134244317030305301444269232291818324946990341635905384116709933493170
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 33997028 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
0.i2c_target_unexp_stop.5485979551220768610336569782035313874150623759646777643461748245512553033993
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 190811759 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 190811759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.94139733944034338752734577276078512416131050984688597058287450427296890613944
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 394543400 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 394543400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
Test i2c_host_stress_all has 3 failures.
1.i2c_host_stress_all.99043668481162498946030844832716630424077905394508211895935926034217075518334
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:a836e983-275c-49bf-be3d-6607500d07e4
22.i2c_host_stress_all.1185096303917765831662952728499078055279071645666124303237278771663275613943
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
Job ID: smart:15218ec7-c3fb-48ee-9f12-e048e535b3be
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
3.i2c_host_stress_all_with_rand_reset.8195693687902442695217007549107888393269320990479696411524676456691448159501
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:182c7304-c750-4d18-9e3b-cff397973435
Test i2c_target_stress_all_with_rand_reset has 2 failures.
5.i2c_target_stress_all_with_rand_reset.93125261204179269259930411737331847368711511848407088661412710920141733185426
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:49576bfd-bed8-457c-927d-3a57a720e16c
7.i2c_target_stress_all_with_rand_reset.37402638999756792307295660980509140283171950955598552548768503449219317380957
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ce2739af-292f-4211-bb95-f221b0525a6c
Test i2c_host_perf has 1 failures.
38.i2c_host_perf.75813304871981308797797515923291128740625721385105526993048421836304311234541
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_perf/latest/run.log
Job ID: smart:32f6c67d-b8e0-4bbb-ab6a-8e59e27f2b33
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
4.i2c_target_stretch.36732065570864843789790463162369756395209289853640728558678557259267217149987
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10003012568 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10003012568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stretch.12529543092847672602164592122251898052919265586812963312501582891436452749981
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10050255313 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10050255313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
0.i2c_target_stress_all.22628281610371940620669834554427619817090624024881546103005160822078179214505
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 14799580664 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 14799580664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all.89622368180915062412364099129212677074357761239918299254010482267293288384745
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 18744683068 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 18744683068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test i2c_host_error_intr has 2 failures.
6.i2c_host_error_intr.115752771661339668593289751318510385836145599302215711832488128722014016294583
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_error_intr/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_host_error_intr.40065587549683308898891134322773761905442963481111343866235249959803625330814
Line 298, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_error_intr/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
15.i2c_host_stress_all.25159116389508553106919801909149636751794274005172722290730703467966745001286
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*) == * has 3 failures:
14.i2c_host_mode_toggle.41947046734826605742646746809230402966012040557105407025357677298462546979523
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 69038119 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xca99cd14) == 0x1
UVM_INFO @ 69038119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_host_mode_toggle.80351442724989885983969887283779807182564349490091575506419233937896812762290
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 53087197 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf1a6ac94) == 0x1
UVM_INFO @ 53087197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
24.i2c_host_stress_all.60636022194369933469763226164968781952653946326340740951474451200512521713538
Line 417, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 68993173284 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10485847
43.i2c_host_stress_all.90060458899279419302778231593708325178513222650926521731061597692980927822893
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 47167720290 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1870601
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
17.i2c_target_fifo_watermarks_tx.114240085122590995789130009995038233254213293878997016987149083306923849118936
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
46.i2c_target_tx_stretch_ctrl.17955476047916643801216836706782771560562919877809384962341108407203343848261
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (cip_base_vseq.sv:749) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
2.i2c_target_stress_all_with_rand_reset.51848197285106530153660203109545725943999952954651128840142842196965614323292
Line 528, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111059279482 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 111059279482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
21.i2c_host_mode_toggle.80347594175202166542436770530027543439564055741766516952948818396702627043534
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.