8b2da8db5e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.962m | 8.533ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 39.250s | 3.021ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 31.438us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 41.746us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.360s | 529.009us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.830s | 40.058us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.890s | 117.952us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 41.746us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.830s | 40.058us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 19.650s | 2.742ms | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 49.457m | 40.595ms | 21 | 50 | 42.00 |
| V2 | host_maxperf | i2c_host_perf | 50.747m | 51.869ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.750s | 48.097us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.517m | 51.739ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.343m | 5.211ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.450s | 524.428us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.470s | 530.921us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.440s | 838.995us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.233m | 2.978ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.360s | 3.755ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.490s | 156.785us | 14 | 50 | 28.00 |
| V2 | target_glitch | i2c_target_glitch | 11.750s | 2.200ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 38.978m | 49.614ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 7.540s | 998.826us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.414m | 3.980ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.250s | 3.687ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.880s | 932.911us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.150s | 348.921us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 58.225m | 68.359ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.414m | 3.980ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 12.185m | 27.499ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.830s | 6.596ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.074m | 3.583ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.850s | 5.077ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 35.000s | 10.178ms | 28 | 50 | 56.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.330s | 534.125us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.670s | 1.389ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 50.747m | 51.869ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 38.659m | 24.297ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.360s | 3.755ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 12.300s | 976.573us | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.270s | 669.560us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.950s | 2.313ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.720s | 695.838us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.270s | 1.543ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.620s | 559.326us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 30.652us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 18.098us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.960s | 196.886us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.960s | 196.886us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 31.438us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 41.746us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.830s | 40.058us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.210s | 62.976us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 31.438us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 41.746us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.830s | 40.058us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.210s | 62.976us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1678 | 1792 | 93.64 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.420s | 560.992us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 131.975us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.420s | 560.992us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 12.145m | 8.354ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.490s | 1.472ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 19.815m | 189.094ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1858 | 2042 | 90.99 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.38 | 97.30 | 89.76 | 97.22 | 72.62 | 94.40 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:
0.i2c_host_mode_toggle.2734654882448637010838096585562410715343265598570673707383655869554795525395
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 126818447 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @30576
1.i2c_host_mode_toggle.61809800204771598315023258184178952095859371235021243431025017044955576184506
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 1154107463 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @48420
... and 17 more failures.
1.i2c_host_stress_all.17732456316179358439607310471239755498569782243102418701277693840051730364962
Line 417, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15057425187 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3506841
3.i2c_host_stress_all.17529009825671325917499350274488122367262202809644057147338074907481995367144
Line 393, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 155981065302 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18629059
... and 17 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
0.i2c_target_unexp_stop.13639969426649915171833317897921460633389120980204599217634959800041221534012
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 401855191 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 162 [0xa2])
UVM_INFO @ 401855191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.82004397584564682663778875935047975465919707295440188146200714173704665949617
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 98936022 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 9 [0x9])
UVM_INFO @ 98936022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
5.i2c_target_stress_all_with_rand_reset.60435368824554955878418761989099497273392576518249783376278081472432806748751
Line 857, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 147792497228 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 223 [0xdf])
UVM_INFO @ 147792497228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
4.i2c_target_hrst.108625993127431335928036557633727272938464817629109753795887041446891626707680
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10021881389 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10021881389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_hrst.38101716336341406208928233064665898258178172835652757938580260509492423551619
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10005252443 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10005252443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.42545222830216886313833613812116412209311514458575175166308198061979709694005
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16149496144 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16149496144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.54182097123018159410003272024299951646871332104360210380698410869221623452198
Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2184095926 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2184095926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_stress_all_with_rand_reset.107893447115161894511344327470283138457797188989835926142475896072535897729792
Line 488, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 67174671106 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 67174671106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.77190642918521291852706440879637493593521646916238725750011666831122913996980
Line 679, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23135578831 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23135578831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
3.i2c_target_nack_txstretch.110160288867045409373593601408176347521962784654601681090953141486233678313280
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 303002028 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 303002028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.49302659743253665537163061318533097193777279783522152443717696872470123155441
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 543545347 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 543545347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 12 failures:
14.i2c_target_unexp_stop.99378783667032736119645612821628069313837881772693681765244552697572687334348
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 319298105 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 319298105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_unexp_stop.1978163176009586518288351116125935876183417936626165786943220458520336334994
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 49145507 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 49145507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
6.i2c_target_unexp_stop.46072428414206906785574539469996720881773428980924049826938319262790823839871
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 738940950 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 738940950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.44771913678318464837520049143883104119481517484657933007364914091884706575877
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 137495861 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 137495861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:
2.i2c_host_mode_toggle.57136663205547664097593047185109258944051513492560323912600655963138348582442
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 84855745 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
11.i2c_host_mode_toggle.69463699724400118888307632167138886717594198349508676344851616112990053959951
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 34937806 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.90791148426430584259539100121952919894337115827227859602913901087826404402472
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:37570ea3-2e6d-451a-ae0e-a5ad68cc2fba
Test i2c_host_stress_all has 4 failures.
9.i2c_host_stress_all.26525622383861581161708443551070583371204740409179930094186528602373017105412
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job ID: smart:3f3ef506-6048-4c3e-b052-954f26643569
17.i2c_host_stress_all.25317570486135362014415123848761689137154942468307970272172991333212787025259
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
Job ID: smart:a6b669f6-4e45-4cb4-825e-c78f3fecb99e
... and 2 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
9.i2c_host_stress_all_with_rand_reset.104632732677387331100666552326341462795489422289859467915729658210130950669586
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:15f81457-c068-48f5-a5fa-de06f7dd092a
Test i2c_host_error_intr has 1 failures.
21.i2c_host_error_intr.59518204269544873464626402186047621814258839278378909495531465323154266041846
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_error_intr/latest/run.log
Job ID: smart:2e26990f-0328-4cda-8752-ef740f28f726
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*) == * has 7 failures:
3.i2c_host_mode_toggle.25992272224961222610205707868307587415936186389776425057853579939197598375629
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 19469407 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x56fefc14) == 0x1
UVM_INFO @ 19469407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_host_mode_toggle.36665902566698435910166175876242815594202312615819050619208179691891353536805
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 30792078 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc19b8594) == 0x1
UVM_INFO @ 30792078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
13.i2c_target_stretch.64934099196515506947594016883300201490859109456950208369411273744216806692889
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10053174976 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10053174976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stretch.93217019842217840272625606804365529792125755939462520551125930121629990191541
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001735796 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001735796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:
2.i2c_host_stress_all.40420385743459245271997919484926361333919751187343549942873136800167444631607
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 69279767626 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4515823
6.i2c_host_stress_all.105161469737012533630754894376360363762469718239612076755174765706637236582100
Line 398, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 40595338736 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @51741401
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
6.i2c_target_tx_stretch_ctrl.69315642883960335956472913345946972456416349765914679521240695209968171736928
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
38.i2c_target_tx_stretch_ctrl.107649508120171315692878249623789696622844827325537739326486561138711920974546
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
21.i2c_target_fifo_watermarks_tx.93787386494497596035691936472741597661436398526618748450323049621622629747412
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred! has 2 failures:
6.i2c_target_stress_all_with_rand_reset.51991551461734413349490967601335777409860139281919653698807588894986373166682
Line 641, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 44578342628 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 44578342628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.11737650078686917309150628618014749633734973259212673346001045628053160799436
Line 1000, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 189093969411 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 189093969411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
2.i2c_target_stress_all_with_rand_reset.57742046324806514348450862863925628619385544270860011241090570017182914349766
Line 458, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 100862863297 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 100862863297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
17.i2c_host_mode_toggle.93269448864015231510301592418229981725990528626686885858662090112948466200676
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
26.i2c_host_error_intr.8897444801608535303267090408654240767758573833200240624765766088192267767863
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 311859767 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
28.i2c_host_stress_all.48320492015888761118768979343260254500379824091564059993879272463981874253510
Line 362, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---