974aaab627| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.909m | 2.110ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 36.120s | 1.131ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.860s | 71.907us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.860s | 247.540us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.140s | 278.622us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.790s | 531.016us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.390s | 30.658us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.860s | 247.540us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.790s | 531.016us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.660s | 1.474ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.063m | 38.405ms | 10 | 50 | 20.00 |
| V2 | host_maxperf | i2c_host_perf | 48.262m | 49.163ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.760s | 41.778us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.608m | 5.194ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.532m | 16.090ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.390s | 1.804ms | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.720s | 1.222ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.530s | 966.580us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.153m | 4.048ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.360s | 3.648ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.810s | 718.108us | 18 | 50 | 36.00 |
| V2 | target_glitch | i2c_target_glitch | 11.300s | 2.100ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 41.597m | 52.783ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 7.590s | 2.166ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.184m | 8.121ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.420s | 14.478ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.930s | 282.137us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.930s | 1.421ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 45.211m | 69.667ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.184m | 8.121ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 13.426m | 25.890ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.080s | 11.314ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.823m | 4.717ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.270s | 11.314ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.360s | 10.318ms | 29 | 50 | 58.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.530s | 748.812us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.630s | 170.613us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 48.262m | 49.163ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 3.166m | 5.947ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.360s | 3.648ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 17.650s | 1.497ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.230s | 4.834ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.020s | 1.247ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.660s | 867.785us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 25.240s | 5.159ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.580s | 572.077us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.730s | 18.017us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.790s | 26.632us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.970s | 659.313us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.970s | 659.313us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.860s | 71.907us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 247.540us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.790s | 531.016us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 96.243us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.860s | 71.907us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 247.540us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.790s | 531.016us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 96.243us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1677 | 1792 | 93.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.350s | 256.349us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.040s | 83.356us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.350s | 256.349us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 8.505m | 9.919ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.210s | 720.547us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 19.745m | 65.864ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1857 | 2042 | 90.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.27 | 97.21 | 89.76 | 97.22 | 72.02 | 94.26 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 40 failures:
0.i2c_host_stress_all.111351861029607319840208042477550323195458624262667788092371830570225893891502
Line 343, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 38405032791 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9651491
2.i2c_host_stress_all.54060242010632769836666320237261266906268616954605287882421647600191088640353
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 64625674876 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5442821
... and 25 more failures.
1.i2c_host_mode_toggle.61062409066533487759940718060250825944544312357168280075256198844428823416514
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 294578992 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10788
3.i2c_host_mode_toggle.105818815260661063301105873774058578903707298759728430549088151605216838823474
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 99926539 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @54140
... and 11 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
0.i2c_target_unexp_stop.38869545288997649247872077514016302274408562473405884529047205081485610480570
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 57503045 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 95 [0x5f])
UVM_INFO @ 57503045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.43123470133388598066763615909803431377897613908671866122397032333745959972853
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 102498646 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 184 [0xb8])
UVM_INFO @ 102498646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 21 failures:
1.i2c_target_hrst.24372170149486006391802141857008110889287919528485526561454352289716160551860
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10024748653 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10024748653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.12967634014846996761596928634015506899449402731194587699282820198211651428381
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10233229578 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10233229578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:
9.i2c_host_mode_toggle.75873537753221911999139040991902906079822631729330971319946494159204251077264
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 148586957 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
14.i2c_host_mode_toggle.53585311384554440451966909352149056743241387485972927365221816879013277094373
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 51327870 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 13 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.19892553592488967527139643715489666758773411226963302091377383718681343807508
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 389939486 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 389939486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_nack_txstretch.32608266960369762830427841370081040195930983889095775288310741238024404463097
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 867785483 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 867785483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
0.i2c_target_stress_all_with_rand_reset.46092250789429096273314429887703620663102609876681255826914037759004279941696
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5660740958 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5660740958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.97519570558833261752102520851203751037896935648062141696644818001520147442960
Line 607, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 65863520622 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 65863520622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
1.i2c_host_stress_all_with_rand_reset.11792652982137942327018466052106434411383647378822496827482083847518406274427
Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5292070638 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5292070638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all_with_rand_reset.11432459194422204436332148440425167799295219325155385934232285367742207142554
Line 346, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 73633411911 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 73633411911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
3.i2c_target_unexp_stop.105479736424265560804873729385766044069232533708314140912491019877014590900419
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 73427153 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 73427153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.42301915853065166175347000656171971176387024920221165909156980079555523458092
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 170567599 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 170567599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
Test i2c_host_stress_all_with_rand_reset has 2 failures.
0.i2c_host_stress_all_with_rand_reset.41869661583335488531590084209535518878728910716308283501596704424455814145072
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9906607f-4325-469d-be1a-facb9f14a8de
2.i2c_host_stress_all_with_rand_reset.27990211316034663699977599631687646458916601384683399353782944370029710819217
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8104a42c-1164-4488-935b-0d304b4518d7
Test i2c_host_stress_all has 4 failures.
1.i2c_host_stress_all.59429333205700433502871064452723264524628516598145356137514403810488537504052
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:51fe2d6e-a949-40a2-9cc5-a5c03c7349a1
6.i2c_host_stress_all.77015453094846755228398898186877889106602715806768878534733853839477350938063
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job ID: smart:a808b9d1-8bef-4421-9c8b-8e57a95e9f33
... and 2 more failures.
Test i2c_target_stress_all_with_rand_reset has 1 failures.
7.i2c_target_stress_all_with_rand_reset.19260689276669961146958279340910299768676086269579130417717950544341356200727
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:070b45c7-d3c9-47ea-80a7-297e447a5013
Test i2c_host_perf_precise has 1 failures.
13.i2c_host_perf_precise.54901886258394267473722069169198602470074833906006828041326441360082819474131
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_perf_precise/latest/run.log
Job ID: smart:fc3f08cd-1904-4190-aaa7-ed7fe93f76cb
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:
1.i2c_target_unexp_stop.47851691926686857298627418243541601952658131485919214971282428816069768266462
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 300696750 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 300696750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.60447188862758855329309365717330708441284592145143987690176570151510054136595
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 48493543 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 48493543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
9.i2c_host_stress_all.87650929867220557694881913277144523250862672273014734506109223207072372347998
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 43538002565 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1933577
14.i2c_host_stress_all.77297913338964521238728533928983624116979191338957246574706175329869304450218
Line 372, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 46057196304 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2082379
... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 4 failures:
1.i2c_target_stress_all_with_rand_reset.88244006940402707103034311990529168839835287363090235081369203858143380506388
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5137620849 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5137620849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.20845141526929127458393325967421863640545775993273464126413094248744901428431
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19892160007 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 19892160007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
16.i2c_target_stretch.88240156902253799779287659153643089984349967330993842143150887326146296442256
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10020067609 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10020067609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stretch.503803758142057608961066468436295908195683121269128660145974007065401531293
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10024063602 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10024063602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
0.i2c_host_mode_toggle.77080612275942926681956161414222386487836239074381126762146589955047877492605
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 303319806 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xaaf2a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 303319806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_mode_toggle.103008884527660761700989597472483482166804651418890332391821345713615320611513
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 104972412 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe0f58614, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 104972412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_fifo_watermarks_tx has 2 failures.
23.i2c_target_fifo_watermarks_tx.28159335008373127851500213697506769873309854109354389367866878302338759887582
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
32.i2c_target_fifo_watermarks_tx.101837932971118094161781594736551575764871678601869419967286435878199952403672
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
38.i2c_target_tx_stretch_ctrl.38863573990774101086155838497651181629775366438467368950049259936793546201572
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
31.i2c_host_stress_all.86326009970815224752468372058417918606710865064232845148886019078604192841121
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_host_stress_all.95983640395557389655532302399924110075167388993009077289263664578626516310043
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
13.i2c_host_mode_toggle.58989611472649219856121515966047480790132197352460605256136683243873208101346
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
32.i2c_host_stress_all.91509063353405836353265190703470669222714415422883922382053601632003218399574
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8443643694 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
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Name Type Size Value
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