e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.692m | 8.034ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 37.930s | 4.718ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 43.607us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 25.979us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.770s | 1.394ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.920s | 76.001us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.670s | 60.109us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 25.979us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.920s | 76.001us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 15.500s | 397.128us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 49.026m | 38.921ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 57.592m | 18.551ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.760s | 112.342us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.383m | 19.508ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.408m | 9.633ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.320s | 648.419us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.010s | 1.818ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.860s | 250.128us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.786m | 15.252ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 41.710s | 1.847ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.410s | 931.376us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 11.900s | 8.554ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 47.520m | 44.810ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 7.630s | 1.880ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.149m | 5.962ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.680s | 23.416ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.950s | 299.314us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.960s | 1.806ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 44.521m | 60.866ms | 49 | 50 | 98.00 |
| i2c_target_stress_rd | 1.149m | 5.962ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 11.900m | 21.850ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.310s | 1.353ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.197m | 4.483ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.090s | 6.930ms | 48 | 50 | 96.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 33.980s | 10.019ms | 26 | 50 | 52.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.540s | 1.340ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.640s | 194.089us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 57.592m | 18.551ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 13.773m | 24.237ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 41.710s | 1.847ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 16.930s | 1.267ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.270s | 3.038ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.090s | 2.558ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.700s | 355.216us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 32.200s | 1.997ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.600s | 1.196ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.710s | 17.412us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 54.667us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.620s | 119.380us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.620s | 119.380us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 43.607us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 25.979us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.920s | 76.001us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.300s | 66.415us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 43.607us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 25.979us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.920s | 76.001us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.300s | 66.415us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1674 | 1792 | 93.42 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.520s | 130.506us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.020s | 246.777us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.520s | 130.506us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 14.261m | 31.821ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.670s | 740.001us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 11.768m | 426.777ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1854 | 2042 | 90.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.98 | 96.88 | 89.46 | 97.22 | 70.83 | 93.90 | 98.44 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 49 failures:
0.i2c_host_stress_all.81718080757044719106123938296626093718875178820838119758053926429568848030137
Line 436, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10656685556 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2255071
1.i2c_host_stress_all.21698217254047523635987086066494926421463993512050855103732483052838893134451
Line 403, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18487779932 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17926049
... and 28 more failures.
2.i2c_host_mode_toggle.103232980344359724219616828357824966043563756899222046540502968764390861476120
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 974418631 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @75920
4.i2c_host_mode_toggle.89722730616737817252284445161284664976795353438795443311764606816313237029829
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 122442574 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @95812
... and 17 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
0.i2c_target_hrst.87431283504477283721333842300940463371109945701498357820385429743815312053488
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10018992906 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10018992906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.54496794342590590400845923030688045925383672117796710837159094815331612569559
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11324379502 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11324379502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 21 failures:
0.i2c_target_unexp_stop.90045351210999180077814431119141066863232641103118768560571392482834743615282
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 485811383 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 223 [0xdf])
UVM_INFO @ 485811383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.74784824826911902886183104758008767517915779866953424889928655055817614265173
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 601283405 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 51 [0x33])
UVM_INFO @ 601283405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
2.i2c_target_unexp_stop.49714529119097735903817360621465921449475214951352295596279760110396469056007
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 113948948 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 113948948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.62437977111129770891733650663336197406433429296999833447603916341273621339542
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 435993897 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 435993897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.63472537440687606038872788873022694357428082401957779471186544809633900600976
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5641135667 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5641135667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.93738952243363364912171191204764110429257367970523096727292173653917968801512
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1391194161 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1391194161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_stress_all_with_rand_reset.26439665626614155219595710193610694337621793635405839389563803444826757701489
Line 542, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27589262468 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27589262468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.9266662432554863645388347134971407797327040637306696062266668569130497150027
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2019338476 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2019338476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.73629128705883777927635461971136321984993835676996465581074912984673164905380
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 189836155 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 189836155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.70948118212294368676434744240684965834070931986219947912836674155741252595730
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 726500954 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 726500954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:
4.i2c_target_unexp_stop.106606105000077167553887203394461178892247084638096475388823657795668867815611
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 995525147 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 995525147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.85520784321721410030947975369129250955641680687764736203590940566302897028713
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 396409885 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 396409885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
Test i2c_target_stress_wr has 1 failures.
1.i2c_target_stress_wr.104465206035840793078831693001933116124082988464445590867935034811025035347876
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log
Job ID: smart:a8385932-ded9-4020-8945-139249dbffdf
Test i2c_host_stress_all has 4 failures.
3.i2c_host_stress_all.72098049566545275944507868588097299184790550596591673841071781649780628270216
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job ID: smart:891af51c-5c2c-4bd4-9f37-cc47fdd0683d
6.i2c_host_stress_all.39540315251724727596590186230716397268908526842914053328246959589369945108084
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job ID: smart:a1ab0821-8d33-42b9-8b85-f8f4af8e82c9
... and 2 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
3.i2c_host_stress_all_with_rand_reset.48843485540505360638632738280972446033420302880050030509592528364585013437836
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ad9aa05d-cc0f-4c3c-ba14-e3c8a41faa1a
Test i2c_target_stress_all_with_rand_reset has 1 failures.
5.i2c_target_stress_all_with_rand_reset.95104752830319751914730481641753814903943099515896801002368031199720385366092
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:82c0122a-edd3-429d-8158-3d3863bcab76
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 7 failures:
3.i2c_host_mode_toggle.28718696882565547330469983546626885764423425315570411317773848855954902378319
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 60704844 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
10.i2c_host_mode_toggle.30842606251345729042404139753862074036788691845777535367102978459081200125156
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 361784964 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 6 failures:
5.i2c_host_mode_toggle.85659350907693510335137126771383442415928480324190561693298694586787151069817
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 48900580 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x611e6914, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 48900580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_host_mode_toggle.62327534358348867948846492638249164397391507506141901377084099595249673457961
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 86164955 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x16e2ee94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 86164955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
9.i2c_target_tx_stretch_ctrl.109884414345944212936355223529691937578598461875435797746940578275427442474833
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
12.i2c_target_tx_stretch_ctrl.11322829803177004669152530014486994562300244113144581078093251935385721159634
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
14.i2c_target_fifo_watermarks_tx.24418392753078033941497497953004311403260452978811463941025190517157731486629
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
15.i2c_target_stretch.13840154268283999544897988410332467707332002233575888066526079198958427079042
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012047131 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012047131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stretch.39654329478092807478878951563640095627177621211713272438147071096375605039929
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10051621607 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10051621607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
31.i2c_target_bad_addr.37777184855098525490143151236705866995990593931480651905006377990191200047032
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.i2c_target_bad_addr.31085041273165203280896210089760190032601208742745424812395513382930834977031
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
0.i2c_target_stress_all_with_rand_reset.54106340627532979289923364936847118996280044830701390477244310275008023358148
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26732359867 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 26732359867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
33.i2c_host_mode_toggle.114445957594906297011516797308126879241705214592174813558058346953551767877292
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.