e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.882m | 2.007ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.750s | 1.465ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 37.441us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 5.160s | 2.272ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.130s | 2.151ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.890s | 364.751us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.490s | 53.572us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 5.160s | 2.272ms | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.890s | 364.751us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 20.420s | 477.155us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.212m | 95.792ms | 19 | 50 | 38.00 |
| V2 | host_maxperf | i2c_host_perf | 37.749m | 49.617ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.750s | 83.559us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.745m | 6.797ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.540m | 5.639ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.290s | 115.171us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.340s | 3.702ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.530s | 458.348us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.962m | 6.863ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.450s | 1.041ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.300s | 198.184us | 22 | 50 | 44.00 |
| V2 | target_glitch | i2c_target_glitch | 11.070s | 2.588ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 29.068m | 48.233ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 7.360s | 948.939us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.310m | 1.741ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.500s | 1.415ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.930s | 778.686us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.960s | 539.326us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 30.849m | 55.793ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.310m | 1.741ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 22.353m | 32.762ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.420s | 1.688ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.144m | 6.134ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.900s | 6.705ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.220s | 10.135ms | 25 | 50 | 50.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.430s | 2.319ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.670s | 174.913us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 37.749m | 49.617ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 32.312m | 23.223ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.450s | 1.041ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 19.890s | 1.728ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.390s | 624.263us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.010s | 2.549ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.710s | 329.488us | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 27.790s | 2.692ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.690s | 573.297us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.750s | 18.268us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 24.877us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.590s | 552.786us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.590s | 552.786us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 37.441us | 5 | 5 | 100.00 |
| i2c_csr_rw | 5.160s | 2.272ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.890s | 364.751us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 27.697us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 37.441us | 5 | 5 | 100.00 |
| i2c_csr_rw | 5.160s | 2.272ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.890s | 364.751us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 27.697us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1678 | 1792 | 93.64 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.550s | 3.649ms | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.980s | 113.477us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.550s | 3.649ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 9.374m | 7.694ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.100s | 889.797us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 18.337m | 45.713ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1858 | 2042 | 90.99 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 26 | 53.06 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.50 | 97.49 | 89.88 | 97.22 | 73.21 | 94.47 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:
1.i2c_host_mode_toggle.24112708835060765334681111146268173762247381370089894797988560035943778458863
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 198183786 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @79114
7.i2c_host_mode_toggle.82274638356841731489703769713281922647667188853174736671672353544700889870021
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 551916884 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @38016
... and 12 more failures.
7.i2c_host_stress_all.109429661138913848318783053929536637154142832396009755127224877113860451737585
Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 126480899601 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @36845809
8.i2c_host_stress_all.67533576602324883047672704722867725134921571375921632188009554734976665589897
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 72288527835 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14260483
... and 25 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 35 failures:
0.i2c_target_unexp_stop.111589429838782866771647103631505182813003932676853700911700388696634423947290
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 768360473 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 20 [0x14])
UVM_INFO @ 768360473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.114817862588736612203210537949388123109628536114320644531692976246455823216319
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 497642543 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 20 [0x14])
UVM_INFO @ 497642543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
8.i2c_target_stress_all_with_rand_reset.64698008006677866900435626727351492904073767718744933928927562246153020320407
Line 411, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14379111785 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 56 [0x38])
UVM_INFO @ 14379111785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 25 failures:
0.i2c_target_hrst.29066696440715665291108488108861893409355083684253417538991825586942296345185
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10059582546 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10059582546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.8079017571008178828960471541945376473062815869027491390096040093410766631369
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10290219138 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10290219138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.1553728700081808000203845958819497316408461437604619658946887708710114582816
Line 311, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 60901585418 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 60901585418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.42466002141731681674686390941372194659960834266765438774129443405128220263741
Line 304, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9954252850 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9954252850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.i2c_target_stress_all_with_rand_reset.98839702171520380738269541177503044499605293670840276069043734083333242582438
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3036707399 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3036707399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.43311311415021642166185231006955679591631644478429682326854922707018109870112
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4816720148 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4816720148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
1.i2c_target_nack_txstretch.102458512350397686717416408572965150471044554502472510504459910885750090988987
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1739068564 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1739068564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.54661301552957174141249122215926241989625579394181687242246806029837280328291
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 840270131 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 840270131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 13 failures:
4.i2c_target_unexp_stop.60689924647647266309506146980410089693869932933986681227663086450635010693295
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 196460167 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 196460167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.46523897399628148101582599017856707515960850879854807103275635986149790146294
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 126477322 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 126477322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:
11.i2c_host_mode_toggle.9206057039870275701011574619888676421972466725721629024902284114400893485332
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 170376762 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
21.i2c_host_mode_toggle.61851379157019603222024981857900241973914187283913558668043277132662399000446
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 67721782 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 9 more failures.
30.i2c_host_perf.54767470405719771475647096949699279285861075819357516739679911467368996067193
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_perf/latest/run.log
UVM_ERROR @ 211038689 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
18.i2c_target_stretch.10867054232732336096042518805358599100881375873370778368999883501427455592652
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10013537239 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10013537239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stretch.2946920216713714771329087460919748890720227139733991956536311285399410883569
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002436767 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002436767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
2.i2c_host_stress_all_with_rand_reset.45324974198874738446388687965812863255636493942512198787555675343522701174143
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2d360d60-4a34-4c4a-91ab-21bcc20c91a6
Test i2c_host_stress_all has 1 failures.
6.i2c_host_stress_all.77444105183594859903661791433250109991899151776717005891240795859233241968703
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job ID: smart:1f80b27e-2ed9-42e6-8888-9840c0230e8b
Test i2c_target_stress_all has 1 failures.
22.i2c_target_stress_all.77694123342459418473030892389254967256203141846046554746741863526831666772971
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
Job ID: smart:0f01ab18-adfc-4dd1-8ca1-3d85a74e0181
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
9.i2c_target_tx_stretch_ctrl.15754619587475580945190720937028215088059252535349794279148916946240849870865
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
38.i2c_target_tx_stretch_ctrl.7052797847670836989290036271888138545686899619038644802489941923457395973652
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
30.i2c_target_fifo_watermarks_tx.806827334903126670859116057559362326991177368382472380508345697113546557933
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
34.i2c_target_unexp_stop.101330370006819801788218901304672076719420412453851012226956779878536642359286
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 273780122 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 273780122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.i2c_target_unexp_stop.1663334772700721664846391841924243347733911510767251909380866594287648651348
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 204698767 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 204698767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
0.i2c_host_stress_all.69154724175555888853466043966837901721728391806563054501703950496730580437811
Line 376, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 37284965485 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3487959
22.i2c_host_stress_all.23866036411980994976419292717725137257308870195404780551430879719567792194167
Line 358, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 48783139966 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2730061
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
9.i2c_host_mode_toggle.33655773879422978245903277012468374583154570490027778709531268107628524422295
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 107090280 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x9b0fc414, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 107090280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_host_mode_toggle.8025570504168670655678934840730451346430009836290993360771847271736709168711
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 49627214 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe0d8fa14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 49627214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
Test i2c_target_stress_all has 1 failures.
42.i2c_target_stress_all.100991140944016502997194812085424693065262628085700324445554165290302172777222
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 48232866938 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 48232866938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_intr_stress_wr has 1 failures.
46.i2c_target_intr_stress_wr.48367993081297312313586891999096469398697551721173886623343300749726204892515
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 47326805022 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 47326805022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
0.i2c_host_mode_toggle.41101351069634467873599777857180630846090978146461422428118138520195670973827
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=69) has 1 failures:
9.i2c_host_perf_precise.59811250625555933607843723844221654579770730703951488733031460531021823408348
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 10067471034 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x646b7394, Comparison=CompareOpEq, exp_data=0x0, call_count=69)
UVM_INFO @ 10067471034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
17.i2c_same_csr_outstanding.80621127279631382793257831582362468544066754929181013885536932102996003041200
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 69073700 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 69073700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
31.i2c_host_stress_all.62367483333139143062933131789890271410989072187423448181614547481181246690246
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---