I2C Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.785m	4.448ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	51.080s	1.633ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.790s	20.925us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.810s	28.151us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.280s	1.695ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.760s	79.834us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.620s	129.587us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	28.151us	20	20	100.00
		i2c_csr_aliasing	1.760s	79.834us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	7.690s	1.547ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	55.943m	23.028ms	13	50	26.00
V2	host_maxperf	i2c_host_perf	33.718m	49.660ms	49	50	98.00
V2	host_override	i2c_host_override	0.740s	19.215us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.196m	7.957ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.096m	5.170ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.240s	246.814us	50	50	100.00
		i2c_host_fifo_fmt_empty	32.230s	631.385us	50	50	100.00
		i2c_host_fifo_reset_rx	14.660s	253.073us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.415m	3.861ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	47.350s	4.876ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.200s	351.244us	13	50	26.00
V2	target_glitch	i2c_target_glitch	11.650s	2.196ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	39.873m	60.543ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	9.080s	1.150ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.252m	1.632ms	50	50	100.00
		i2c_target_intr_smoke	9.240s	3.367ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.930s	296.726us	50	50	100.00
		i2c_target_fifo_reset_tx	1.980s	292.167us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	44.881m	64.094ms	50	50	100.00
		i2c_target_stress_rd	1.252m	1.632ms	50	50	100.00
		i2c_target_intr_stress_wr	8.355m	19.165ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.190s	5.963ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	4.070m	4.113ms	42	50	84.00
V2	bad_address	i2c_target_bad_addr	7.260s	5.155ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	34.320s	10.232ms	23	50	46.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.310s	707.151us	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.560s	610.854us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	33.718m	49.660ms	49	50	98.00
		i2c_host_perf_precise	28.777m	24.296ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	47.350s	4.876ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	13.530s	1.048ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.520s	684.637us	50	50	100.00
		i2c_target_nack_acqfull_addr	3.040s	2.098ms	50	50	100.00
		i2c_target_nack_txstretch	1.720s	3.651ms	33	50	66.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	34.880s	885.347us	50	50	100.00
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.630s	1.244ms	50	50	100.00
V2	alert_test	i2c_alert_test	0.680s	35.331us	50	50	100.00
V2	intr_test	i2c_intr_test	0.760s	17.299us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.840s	575.099us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.840s	575.099us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.790s	20.925us	5	5	100.00
		i2c_csr_rw	0.810s	28.151us	20	20	100.00
		i2c_csr_aliasing	1.760s	79.834us	5	5	100.00
		i2c_same_csr_outstanding	1.250s	224.247us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.790s	20.925us	5	5	100.00
		i2c_csr_rw	0.810s	28.151us	20	20	100.00
		i2c_csr_aliasing	1.760s	79.834us	5	5	100.00
		i2c_same_csr_outstanding	1.250s	224.247us	20	20	100.00
V2		TOTAL			1662	1792	92.75
V2S	tl_intg_err	i2c_tl_intg_err	2.360s	149.838us	20	20	100.00
		i2c_sec_cm	0.870s	138.244us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.360s	149.838us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.671m	10.362ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.810s	1.621ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	16.864m	22.588ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	70	0.00
		TOTAL			1842	2042	90.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	49	38	30	61.22
V2S	2	2	2	100.00
V3	4	3	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.32	97.33	89.61	97.22	72.02	94.40	98.44	90.21

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 51 failures:

Test i2c_host_mode_toggle has 27 failures.

0.i2c_host_mode_toggle.44224229050547705824861895196158985391997203894108370220403599461786219024051
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 163987472 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @155690

1.i2c_host_mode_toggle.29755220989960589997235279736116947339646838855583550848009880987097915359374
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 341832435 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @47940

... and 25 more failures.

Test i2c_host_stress_all has 24 failures.

1.i2c_host_stress_all.28022257186259527553256754275157801165062240153211362946260516418533961547792
Line 394, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 24451641021 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1517273

2.i2c_host_stress_all.27743751538287782806938075629142909482748724279340871949470591711156142870645
Line 473, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 127561509826 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @15757255

... and 22 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
- Test i2c_target_unexp_stop has 31 failures.
  - 0.i2c_target_unexp_stop.113586887003941591822531104272412436548896734819778215908703570107488449687428
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1621031575 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 11 [0xb])
  UVM_INFO @ 1621031575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.24835024704959084851700194695033529947773431762103538405940221313067696979074
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  55295125 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 8 [0x8])
  UVM_INFO @  55295125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 4.i2c_target_stress_all_with_rand_reset.76057124643028797514073612928471499756545157503960012471278106908511271745568
    Line 342, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27691793862 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 250 [0xfa])
  UVM_INFO @ 27691793862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
- Test i2c_target_hrst has 27 failures.
  - 0.i2c_target_hrst.111214205753271381102058310783867577568921845607336876019029057773150691386762
    Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10013627061 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10013627061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_hrst.92114118227537784253734202369202506080804336139034825648355342564160648506550
    Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10214345466 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10214345466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
- Test i2c_target_nack_txstretch has 17 failures.
  - 2.i2c_target_nack_txstretch.77116848633178221982184821981992647908273870270994926413979096698216901448420
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 154298508 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 154298508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_nack_txstretch.44724359910190553388921757511840987700877316765114684915447020315577441420525
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 151713053 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 151713053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test i2c_host_stress_all has 11 failures.
  - 0.i2c_host_stress_all.57531714659297785926654626704088105093052107167441000990469464136350534000244
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:da4bb735-9eda-4bac-83c1-2f8c22aa9650
```
  - 6.i2c_host_stress_all.75953756778537323560995747385028349722096318160451476479185509641379286228170
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:503a69ee-18c2-46ea-921d-07110cf1eae9
```
  - ... and 9 more failures.
- Test i2c_host_stress_all_with_rand_reset has 2 failures.
  - 2.i2c_host_stress_all_with_rand_reset.69624805199454603317939431639355337832818322756823039863925224153457672642311
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c070c1f3-e9e9-4284-98d4-130b4e250d9c
```
  - 6.i2c_host_stress_all_with_rand_reset.48129661712885924924825839364628274653195119396526618602599929244017783186531
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4ce0dc61-3c14-4bf6-a2f6-1e8256448de0
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_target_stress_all_with_rand_reset.74858325561533587371374999493146471513684197497525255433723451418015105314255
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c3e5e1a7-c26b-419f-ba80-a11f42be41ce
```
- Test i2c_host_perf has 1 failures.
  - 36.i2c_host_perf.26550965086919947162944575251670679068969023507296329315720668517079782297284
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_perf/latest/run.log
```
  Job ID: smart:c8264ce0-d51c-49f5-bb18-59a65163c9db
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
- Test i2c_target_unexp_stop has 14 failures.
  - 5.i2c_target_unexp_stop.744364324459566431403680191221106606454676491833239776604242629827427119246
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 159778552 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 159778552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_unexp_stop.68189275667909801084268146264565282762915274570435779236164270739344755288000
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  12725480 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  12725480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

Test i2c_host_stress_all_with_rand_reset has 6 failures.

0.i2c_host_stress_all_with_rand_reset.64499963583689942607510010680989216827143287374034839258666861437318858913124
Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9907290907 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9907290907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.69339331935168525374635392735555282092887504361814032996256655689853521471871
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1169708695 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1169708695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.50692126397801123046817019212191655269294686510023546346750380021149844692151
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7710602221 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7710602221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.1076683623700436991043225875563693313522162450492730184278172969946811153722
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 41949914047 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 41949914047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:

Test i2c_host_mode_toggle has 10 failures.

11.i2c_host_mode_toggle.25997113935468005012508449502054309817127166070003663890806465748286481161393
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 110323043 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

15.i2c_host_mode_toggle.61774600488854771794462486879693823367799782895392010793670440257066648569775
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 151088223 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 8 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 8 failures:
- Test i2c_target_stretch has 8 failures.
  - 3.i2c_target_stretch.14774547979417656528147208976661998034072547522357051864370057324519671662380
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10028372443 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10028372443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.i2c_target_stretch.9928430092286187644531500179561877202360051306364629137138802783424077150026
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10012617216 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10012617216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:

Test i2c_target_unexp_stop has 5 failures.

4.i2c_target_unexp_stop.9543478950868451354855007240129566604671457196243775697718486665951289171723
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 2013943476 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 2013943476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.i2c_target_unexp_stop.108333347530984035072298333380014224803918060695318356142827509259209732957348
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 160754916 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 160754916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 37.i2c_target_tx_stretch_ctrl.82890049194500833636534774987333970034940034204926315229757292305748901213611
    Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 39.i2c_target_tx_stretch_ctrl.46616580294554238882079352056423755478229576969376978002504792949408838008850
    Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 48.i2c_target_fifo_watermarks_tx.23600009430172310672724682769397517441093953934795460155324773304576568193213
    Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

3.i2c_host_stress_all.29826412768473660636605638252764599843436915546001307867344148866981392963546
Line 491, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19383292305 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4800061

41.i2c_host_stress_all.44972288244318826052150280257501379996147319197312343386276084642022972738894
Line 304, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 74863798032 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4005349

UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 2 failures.
  - 4.i2c_host_stress_all_with_rand_reset.110951722404195191517722397525029449541382811092258821757295449130227807700454
    Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3907455168 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
  UVM_INFO @ 3907455168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_host_stress_all_with_rand_reset.3718708546240213344951293821358396700939628310499473102188863085857506024407
    Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27524833287 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (5 [0x5] vs 3 [0x3])
  UVM_INFO @ 27524833287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.34910910939590043847018167772481919596902012831142314818242685322083064412224
    Line 670, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22588312916 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 22588312916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```