0bfa990ddc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.557m | 1.890ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 50.520s | 8.621ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 49.549us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 25.093us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.180s | 2.175ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.860s | 174.585us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.390s | 126.245us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 25.093us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.860s | 174.585us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 18.310s | 1.488ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 38.200m | 18.889ms | 10 | 50 | 20.00 |
| V2 | host_maxperf | i2c_host_perf | 44.895m | 69.896ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 31.621us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.128m | 22.263ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.120m | 2.464ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.440s | 183.088us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.040s | 941.865us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.150s | 958.353us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.728m | 3.977ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.250s | 1.992ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.890s | 612.130us | 20 | 50 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 11.840s | 2.323ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 30.670m | 55.489ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 8.190s | 4.596ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.140m | 8.602ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.530s | 25.126ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.850s | 787.761us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.840s | 414.653us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 40.465m | 58.926ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.140m | 8.602ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 11.690m | 25.698ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.230s | 17.393ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.249m | 3.811ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.800s | 1.335ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.930s | 10.234ms | 26 | 50 | 52.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.860s | 656.856us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.570s | 158.249us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 44.895m | 69.896ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 33.135m | 24.346ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.250s | 1.992ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 10.510s | 800.805us | 41 | 50 | 82.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.380s | 2.190ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.270s | 646.463us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.740s | 2.140ms | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.520s | 3.190ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.580s | 541.597us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 91.407us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 37.281us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.960s | 493.962us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.960s | 493.962us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 49.549us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 25.093us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.860s | 174.585us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.170s | 247.390us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 49.549us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 25.093us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.860s | 174.585us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.170s | 247.390us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1668 | 1792 | 93.08 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.300s | 87.287us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.000s | 61.864us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.300s | 87.287us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 8.123m | 8.376ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.780s | 1.440ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.190m | 64.562ms | 1 | 10 | 10.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 1 | 70 | 1.43 | |||
| TOTAL | 1849 | 2042 | 90.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 31 | 63.27 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.24 | 97.21 | 89.65 | 97.22 | 72.02 | 94.26 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 39 failures:
0.i2c_host_stress_all.79475808135083721186683152595468657479253319327031412703554705469043919392805
Line 413, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 37210220816 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2833919
2.i2c_host_stress_all.57167458379709551345439478963680286314687255447247689520539015406830798734279
Line 400, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 160670282764 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7499027
... and 19 more failures.
1.i2c_host_mode_toggle.63923851765622508637313256073711162276318682047536379937144066578740026639280
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 304877956 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14028
2.i2c_host_mode_toggle.67518461803563546553846342983782279154220445742352762484988428137460723834378
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 158482547 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @27334
... and 16 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 25 failures:
0.i2c_target_unexp_stop.8456554201135241871407555040204657391417282091723736406891156389091091309659
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 82616417 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 210 [0xd2])
UVM_INFO @ 82616417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.94452738878020968118355257031622621533221112810669537782855665011711442252471
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 179161168 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 169 [0xa9])
UVM_INFO @ 179161168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
1.i2c_target_hrst.53356834827777231361951078488788519149833883675557147775805332626407482450756
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10485679982 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10485679982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.15879385543889896529911040755808835121796583164555566770046200921549843408653
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10032917877 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10032917877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_target_stress_all_with_rand_reset.59219451452674580753248175630795491179472916964744991643364794172110164233585
Line 414, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12270356260 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12270356260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.18973103808303781510654824309133190817248074936477996870779715176494749840622
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4683688546 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4683688546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
1.i2c_host_stress_all_with_rand_reset.42523827394924164110948039697733433856835306934042394627935387197787168938714
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29163910065 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29163910065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.79047658238444570127713758753354652960237617315921616086486824728578870536111
Line 359, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34541808950 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 34541808950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
5.i2c_target_nack_txstretch.104305080545682508743489845831538100644522995681627225269313779560041089464362
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 328537919 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 328537919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_nack_txstretch.37546189239196903164727637881575435197718267202723235152202036547591898535823
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 714327505 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 714327505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
2.i2c_target_unexp_stop.68781757212826715019197639146658873480795365744543454320931341653046584687247
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 167441704 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 167441704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.13177897924920058282514060337611596566235079971280088124724385343279941221778
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 104242425 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 104242425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
0.i2c_host_stress_all_with_rand_reset.47436830301658450288916180712029930261418580578780929830338704467597436128182
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f7b57ede-b05e-43a2-b5b8-746b0d873c39
Test i2c_host_stress_all has 11 failures.
3.i2c_host_stress_all.73376456615269028860354138385275023157944077882750855240522800046870851300579
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job ID: smart:9972c28d-3846-46ad-97bf-4bfd48bcd720
11.i2c_host_stress_all.50140887126794911337670440703316180782854361097937251609554837329335386397471
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
Job ID: smart:06bf2cf2-ceb2-43f4-968b-a43a957bd465
... and 9 more failures.
Test i2c_target_stress_all has 1 failures.
39.i2c_target_stress_all.15089090395113690873589302870589043489348221908587425763088188674231929889238
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_all/latest/run.log
Job ID: smart:47898b93-f98a-44d5-9d90-4633ed5f933b
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
6.i2c_target_unexp_stop.97256234729354593503752772746181474842948737056399982279629039805694914770593
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 243601600 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 243601600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_unexp_stop.96988969804899852669770382736987246475221683189387356881663060986709999159882
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1823310014 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1823310014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 9 failures:
1.i2c_target_tx_stretch_ctrl.24435538237887599384896732078259055059177727542565128090084147581601691861140
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
12.i2c_target_tx_stretch_ctrl.92098240657584842792029356600746019544482656885018562027304081625283785837352
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 7 failures:
11.i2c_host_mode_toggle.88840250056230974277229588526188519124541736733109766897734702599451056584723
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 924844957 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
16.i2c_host_mode_toggle.39739649960034763950228670777507536536605128775980259715973854341363594212384
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 38928535 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
1.i2c_host_stress_all.72623981846697390756603078909569832955176654117787739366325558379857644391495
Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16265254368 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3762017
5.i2c_host_stress_all.75475843699303088107163193989473597011373475347435741206165241237812367013301
Line 403, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 58643186107 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4663675
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
4.i2c_host_mode_toggle.23519488334203038017848711486625926834360929119822302377617055508287494769026
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 108314762 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4afc8394, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 108314762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_host_mode_toggle.92791029663857188242461060557651357334297954433403465787625924031450625376274
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 91130927 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xfce6b694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 91130927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
11.i2c_target_stretch.51848079379173169294440272075707668940934773572921978983586371040143243043843
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10044956393 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10044956393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stretch.24997937376935448705381360523651808630405183428274385139040224291289028640180
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10047950617 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10047950617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_env_pkg.sv:93) [i2c_env_pkg::acq2item] Check failed data >> * == '* (* [*] vs * [*]) has 1 failures:
4.i2c_target_stress_all_with_rand_reset.43017627615650449948568236087366276688510011521944222473018289753995503066241
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47450425 ps: (i2c_env_pkg.sv:93) [i2c_env_pkg::acq2item] Check failed data >> 11 == '0 (2097151 [0x1fffff] vs 0 [0x0])
UVM_INFO @ 47450425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
10.i2c_host_stress_all.62487493091841876843338101746140588362945306848442356281881166812226717600266
Line 425, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3122) has 1 failures:
47.i2c_host_stress_all.52248370933655785646710337972244010212052344874976893575121898078170898438107
Line 314, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 176495737391 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x5d021614, Comparison=CompareOpEq, exp_data=0x0, call_count=3122)
UVM_INFO @ 176495737391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---