e439226b6c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.791m | 8.111ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 45.650s | 6.011ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 24.950us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.810s | 77.817us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.980s | 2.051ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.980s | 223.297us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.350s | 52.262us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.810s | 77.817us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.980s | 223.297us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 8.760s | 849.684us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 48.420m | 38.781ms | 13 | 50 | 26.00 |
| V2 | host_maxperf | i2c_host_perf | 33.376m | 75.452ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 89.921us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.530m | 10.023ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.454m | 6.951ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.360s | 176.052us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.990s | 525.877us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.360s | 239.547us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.975m | 3.076ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 40.030s | 1.684ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.310s | 1.013ms | 15 | 50 | 30.00 |
| V2 | target_glitch | i2c_target_glitch | 10.820s | 8.766ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 27.742m | 47.136ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 8.880s | 1.071ms | 49 | 50 | 98.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.418m | 8.669ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.440s | 6.029ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.170s | 692.923us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.190s | 302.546us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 47.376m | 62.707ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.418m | 8.669ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 16.220m | 29.008ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.280s | 1.590ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.924m | 2.405ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.410s | 1.581ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 32.570s | 10.140ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.340s | 1.400ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.610s | 172.725us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 33.376m | 75.452ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 5.041m | 23.266ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 40.030s | 1.684ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 20.090s | 1.844ms | 45 | 50 | 90.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.290s | 2.285ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.160s | 640.556us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.710s | 238.537us | 32 | 50 | 64.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 25.460s | 1.302ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.740s | 586.160us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 25.777us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 17.606us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.520s | 133.165us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.520s | 133.165us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 24.950us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 77.817us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.980s | 223.297us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.160s | 98.346us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 24.950us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 77.817us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.980s | 223.297us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.160s | 98.346us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1663 | 1792 | 92.80 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.300s | 150.694us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.000s | 464.551us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.300s | 150.694us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 8.851m | 17.770ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.650s | 497.572us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 9.567m | 87.536ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1843 | 2042 | 90.25 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.36 | 97.30 | 89.61 | 97.22 | 72.62 | 94.40 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 48 failures:
1.i2c_host_stress_all.27122387366293526925706969495019671820027211906302740685361869542254940812036
Line 366, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16869999712 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13293053
2.i2c_host_stress_all.63462888680499197150315698454018033932290160570250690539950138227556104857607
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 35852218387 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10353093
... and 25 more failures.
2.i2c_host_mode_toggle.66935375855392749592781038508245645934643875911318759986029998627735725827447
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 665373086 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @109266
5.i2c_host_mode_toggle.35300904877287704914505250117371732645844384201604392050685915788631399408719
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 267211837 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @56274
... and 19 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
0.i2c_target_unexp_stop.114028983550718334776444223128106121236167671188558129304754334177551937871484
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 89453989 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 134 [0x86])
UVM_INFO @ 89453989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.59263147362856475878159727452372609321322357171334407957697694694091956962997
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 154972174 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 234 [0xea])
UVM_INFO @ 154972174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
2.i2c_target_stress_all_with_rand_reset.81286645976635147507644589993341740665475116635945580082226143596094007750064
Line 368, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8834704099 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 200 [0xc8])
UVM_INFO @ 8834704099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
0.i2c_target_hrst.104754493846712587051507241679812069636328700872208802765764844297143473182526
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10092412938 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10092412938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.13443776103423430991794697528046464527288286116632759130003056221245193405874
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11265585253 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11265585253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
0.i2c_target_nack_txstretch.109014231358033387543379599282608369739993456123843744983938181356659988877688
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 530095380 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 530095380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.56179472621089966591009237543533360385650572957930197263482554604463801443965
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 156458883 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 156458883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.76018250256171657745467760545291412371740002676244471157021306521226127272996
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 236386712 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 236386712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.39385415347089722601257207855611879149831172844690235416825200802255956891005
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1390272412 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1390272412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.41640696079979615674027926070919262184415577593460232639300342223045168553265
Line 487, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 72613180355 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 72613180355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.49814964218127056520066166522255746233770018150001065328216993717507572803571
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1633363952 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1633363952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
4.i2c_target_unexp_stop.14171268711837619653472794697211556674410492782393107839687046122239541876231
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 148476806 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 148476806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.17070245629107152087305493767870062878917842542708600803293531316514142998735
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 84970251 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 84970251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
7.i2c_host_mode_toggle.95648028130834482696271189976395832474725316778052495434154989063006808703862
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 34064998 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
9.i2c_host_mode_toggle.14058615759675100809781924186520354484921813754688617493305722279149117707236
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 31730906 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
8.i2c_target_stress_all_with_rand_reset.31931604085912242212827363200160105742182401072411222036671763674223009501227
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:33af9ff7-da98-45af-8aee-e7e4007b2209
Test i2c_host_stress_all has 6 failures.
19.i2c_host_stress_all.54267046710375068844047871520237210624803918436348295601295733357566573667306
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
Job ID: smart:65cdceb1-e0ed-44f1-b2ec-44ee7444ae94
24.i2c_host_stress_all.63114630966325110336417684046176247796086268979005004798543270199823545657588
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
Job ID: smart:6b2e4444-6583-442b-a863-dd5e77901679
... and 4 more failures.
Test i2c_host_error_intr has 2 failures.
37.i2c_host_error_intr.85451150604311530865698550060397576472640324401067607163226316187836770287090
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_host_error_intr/latest/run.log
Job ID: smart:e3832161-dc44-47b6-aff6-cd2d2979f758
42.i2c_host_error_intr.41189119487128201690608450197582956685979022950524916571222324427896469615262
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_error_intr/latest/run.log
Job ID: smart:788f03f8-ab5d-430a-b4fa-bbde223dd7a4
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
14.i2c_target_unexp_stop.84134630186128953431261979259115267872461222499297936253533037554131176916709
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 497571787 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 497571787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_unexp_stop.66414421465212647079133919597768133617705923179417411713296959649078581608886
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 140406543 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 140406543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
5.i2c_target_tx_stretch_ctrl.109031017929108459310369412793976130469646395261549551775151429613959172140116
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
16.i2c_target_tx_stretch_ctrl.92848292181827394457988317463843476355507695432751015228778413203644287146749
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
1.i2c_host_mode_toggle.87048052201404725233388186598266054792878353605324494911265086686409330299443
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 42408749 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xd2d38114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 42408749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_host_mode_toggle.38172911805818613226940532263982710231330031865210741918083519887945202536063
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 102510755 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x5a207714, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 102510755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
16.i2c_host_stress_all.67454883595787784117044428926077694435152646713039410627225356941762758801680
Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 25948304173 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2383291
18.i2c_host_stress_all.15209952493810752301030376262121995628845188122101515296441462257531602069413
Line 301, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 35271705942 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7335305
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.i2c_target_stress_all_with_rand_reset.103808396631189948449811084380003149117674263570183012317991811052050583390456
Line 616, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 87536457905 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 87536457905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.30761140110347786544411096723986789152318858253076872139661135152424917098281
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4444631436 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4444631436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 2 failures:
6.i2c_target_stretch.19775584669165697351748295430941927001284148126676022570679042969980292683332
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001922958 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001922958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stretch.7513858885641138755137002211753825412487916398044941529006873512177163202373
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10015875337 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10015875337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
20.i2c_host_stress_all.102094144013250861495061528381488868189644839990474447087870608293529983264773
Line 304, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 28380967447 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
22.i2c_target_stress_all.79708558600585727903730033490364315340658658975902510362259394816552942346662
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 109694710213 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 109694710213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
34.i2c_target_perf.42354231621435685019181794931690722363535329561207787422715408665620219408780
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---