a47820eb4c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.983m | 2.395ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 44.860s | 11.944ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.820s | 27.801us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 25.651us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.690s | 223.018us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.990s | 188.025us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.490s | 377.822us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 25.651us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.990s | 188.025us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 20.790s | 1.694ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 51.385m | 23.709ms | 20 | 50 | 40.00 |
| V2 | host_maxperf | i2c_host_perf | 30.486m | 26.386ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.760s | 29.721us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.710m | 18.506ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.446m | 2.634ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.470s | 773.834us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 21.880s | 1.651ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.560s | 252.162us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.341m | 7.417ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 48.340s | 1.048ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.970s | 431.978us | 23 | 50 | 46.00 |
| V2 | target_glitch | i2c_target_glitch | 11.800s | 2.624ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 49.861m | 64.078ms | 47 | 50 | 94.00 |
| V2 | target_maxperf | i2c_target_perf | 8.380s | 2.086ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.262m | 1.681ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.740s | 7.218ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.910s | 771.905us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.870s | 267.902us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 32.293m | 59.795ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.262m | 1.681ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.659m | 26.650ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 9.060s | 3.207ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.873m | 4.682ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.130s | 5.670ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.480s | 10.004ms | 28 | 50 | 56.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.440s | 551.280us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.660s | 164.580us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 30.486m | 26.386ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 15.594m | 23.260ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 48.340s | 1.048ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 25.580s | 2.295ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.360s | 2.483ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.070s | 616.588us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.680s | 497.608us | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.670s | 7.916ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.610s | 2.022ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 18.837us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 17.909us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.770s | 495.631us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.770s | 495.631us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.820s | 27.801us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 25.651us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.990s | 188.025us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 243.590us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.820s | 27.801us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 25.651us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.990s | 188.025us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 243.590us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1686 | 1792 | 94.08 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.320s | 451.429us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.030s | 147.281us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.320s | 451.429us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 7.422m | 27.986ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.550s | 404.128us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 17.246m | 134.528ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1866 | 2042 | 91.38 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.10 | 97.15 | 89.35 | 97.22 | 71.43 | 94.11 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 40 failures:
0.i2c_host_stress_all.104032521356011852372946585515136366982079816297313362886888178916120305106804
Line 407, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 27145771832 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7214169
1.i2c_host_stress_all.44669734982529659728686389132770723332098939312468265043561818035788617913730
Line 488, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 22297273502 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4592285
... and 23 more failures.
1.i2c_host_mode_toggle.30195437691512084730483000581902554154753913028652308204950913653920358850278
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 179632176 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @55270
3.i2c_host_mode_toggle.38953637269157290992737112589199773521221360674803309424941616796633749907045
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 251320076 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @29358
... and 13 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
0.i2c_target_hrst.21763367822217211021896884641401553718679721699919673896875268609028138473471
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10018924314 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10018924314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.29854126612126804989689981753798181826979586574777357604098662774399825202512
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10137498909 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10137498909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 21 failures:
0.i2c_target_unexp_stop.38120212129502064416793302970202907183634115619079421989266222930943765047314
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 163530071 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 163530071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.114315607825499501457460645722184411382265123549736149777587131444491440124603
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 14178140 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14178140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 20 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
1.i2c_target_stress_all_with_rand_reset.23399353421774165283467400830671520850790563078463327725228340524122434754359
Line 328, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21254945088 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 152 [0x98])
UVM_INFO @ 21254945088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 19 failures.
3.i2c_target_unexp_stop.101446348004934580132653556119871105806656445146647207856309354731479037110940
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 950029514 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 10 [0xa])
UVM_INFO @ 950029514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.50660237909240392106469251329543281652416849844139797425611686191172747552579
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 106162831 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 182 [0xb6])
UVM_INFO @ 106162831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
2.i2c_target_nack_txstretch.41521884955309429507821171412014492155061432532538809402777111328314637711009
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 340619858 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 340619858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.57204444796503535780223997875763228107361692614202413186083146568827291137088
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 203231735 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 203231735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
0.i2c_host_stress_all_with_rand_reset.44287079655446650261279776400173955244136376660013306668099725705984002273707
Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16036870305 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16036870305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.47547872999216444009473455209180747969406083078513175646205972808954924186743
Line 373, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15199012589 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15199012589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
2.i2c_target_stress_all_with_rand_reset.66383526750028758199689053882662731323967805830245595249942060788175519243676
Line 628, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22230845645 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22230845645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.114505301932418669906978129952999056231904769015882288340885436834112571780242
Line 683, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 134528191522 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 134528191522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
4.i2c_target_unexp_stop.111193793203839484488185477228390060339308068343952582798579803877800198177071
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 110349694 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 110349694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.60365586091146181524192900031973276189332080497813450881802634672927474628616
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1068010919 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1068010919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 7 failures:
16.i2c_host_mode_toggle.45100624149772261391987258202526060761025796665513614855241464186963442407718
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 231461127 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
18.i2c_host_mode_toggle.4109250386891660764145224037344204023292268927242366296247799900865053675064
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 194587614 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 4 more failures.
39.i2c_host_error_intr.46718088300227893374850578104980076026028396953001246648119542094060714913741
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 80099507 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
0.i2c_target_stress_all_with_rand_reset.112016856711594740582954392761985258573142596750419626684839561045144322806584
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:908367f2-d527-4c0f-9d92-3cfb35e849f4
9.i2c_target_stress_all_with_rand_reset.21330895990230884244500540491394285014905645346643364391050117232820314883302
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:05928059-d57d-4baf-8e4d-d9e2e3bdbb78
Test i2c_target_stress_all has 1 failures.
17.i2c_target_stress_all.107085878677819383624013053945638683624273020768603634563698249033178220303019
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
Job ID: smart:4238dff2-c4e6-4182-bb47-f58fc1a5db47
Test i2c_host_stress_all has 2 failures.
39.i2c_host_stress_all.54298858287500530235773092006059955544441503382722963794241647905862422038466
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log
Job ID: smart:51ec255a-4467-47b7-bbe4-399e41f988d5
47.i2c_host_stress_all.31869894591588799013898209230231922608880843688843528325117996452727763908958
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_host_stress_all/latest/run.log
Job ID: smart:7c92bc8a-2bc7-4684-9ed0-8e07b359e57b
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
8.i2c_host_mode_toggle.28606611454870486536643552420293027317728433235614634642044771144760927443863
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 58888060 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x756fff94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 58888060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_host_mode_toggle.25409177370506413270101972474618012245294973717080425170771106580555226368144
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 283984925 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xda1f9094, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 283984925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
0.i2c_target_stretch.30773049617614377057377978070069790730319048954928139454853360171245984456201
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002171407 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002171407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_stretch.110292187016075906421062810433840651264459026058067727304318886333522310068443
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002203178 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002203178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
12.i2c_target_tx_stretch_ctrl.85331426216951458095555037219761633508467479323821350934689478635856798254129
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
43.i2c_target_tx_stretch_ctrl.15612495752357099816960878484638519610235538387403273905371607189650343239961
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
15.i2c_target_fifo_watermarks_tx.69047931463208473557811223977221011596031636166119638007171276332376208948021
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
2.i2c_target_stress_all.40274194647055878276222348821206833351353776787090952059027718458606875385513
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 43311377994 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 43311377994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stress_all.95253082157387138086846267111581323071364920482266502540173464224604590116301
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 27175876572 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 27175876572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
4.i2c_host_mode_toggle.24973427865731503849118859197248010204236943474652593571924778697971384740441
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
41.i2c_host_mode_toggle.20638115962707612064350540493279885056949246756337621909389410287994377267793
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_bad_addr has 1 failures.
13.i2c_target_bad_addr.100377130861220743142057486791692446877033229924751713837943281724422739139671
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
36.i2c_host_stress_all.73860223111917207046619999953185617023112035004847891527581797079716436970539
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
27.i2c_host_stress_all.25790845505449021624553146530569981098544885674294906613775697316330533641739
Line 408, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 117789037105 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3697289
28.i2c_host_stress_all.89260448236634673371841512250832061288627889529375646563899644102038201787650
Line 340, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 60872528896 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10935599
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
1.i2c_host_stress_all_with_rand_reset.29246469309301157148886628354795773114888780585950218432778811466286594535576
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21766660728 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 21766660728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
3.i2c_target_stress_all_with_rand_reset.83170104388496755084111799152982086112878781666251521182890346384757045766752
Line 375, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 180054536777 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 180054536777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---