4877b481e8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.628m | 1.984ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 42.410s | 1.408ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 25.668us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.830s | 718.732us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.150s | 5.173ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.870s | 313.663us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.570s | 39.630us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.830s | 718.732us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.870s | 313.663us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 11.010s | 2.222ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.800m | 79.266ms | 20 | 50 | 40.00 |
| V2 | host_maxperf | i2c_host_perf | 50.945m | 74.911ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.730s | 153.227us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.842m | 20.678ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.343m | 16.778ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.330s | 541.187us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.120s | 1.912ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.110s | 947.579us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.990m | 3.124ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 45.620s | 1.052ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.840s | 182.628us | 19 | 50 | 38.00 |
| V2 | target_glitch | i2c_target_glitch | 11.460s | 8.818ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 58.031m | 70.496ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 7.610s | 2.553ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.241m | 5.644ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.890s | 20.869ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.130s | 298.710us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.790s | 265.526us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 43.343m | 64.676ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.241m | 5.644ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.952m | 24.716ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.090s | 19.378ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.975m | 4.000ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.340s | 3.278ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.500s | 10.149ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.380s | 1.165ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.600s | 173.658us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 50.945m | 74.911ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 13.174m | 23.254ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 45.620s | 1.052ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 24.330s | 2.098ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.270s | 530.232us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.060s | 1.092ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.740s | 350.636us | 31 | 50 | 62.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 22.930s | 585.688us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.620s | 9.640ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 19.542us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 148.953us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.290s | 139.177us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.290s | 139.177us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 25.668us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.830s | 718.732us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.870s | 313.663us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 55.166us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 25.668us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.830s | 718.732us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.870s | 313.663us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 55.166us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1676 | 1792 | 93.53 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.360s | 579.885us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.950s | 307.249us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.360s | 579.885us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 12.941m | 6.699ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.850s | 2.702ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 10.857m | 23.922ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1856 | 2042 | 90.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 31 | 63.27 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.23 | 97.21 | 89.42 | 97.22 | 72.02 | 94.26 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 39 failures:
0.i2c_host_stress_all.77383367986807425238975833105799271261322192620784076934429548940381929084137
Line 361, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 55192991309 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @66597427
2.i2c_host_stress_all.21241163945975971706667184403132096527283117979474311869138467937453378124656
Line 346, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 58741684764 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16769571
... and 21 more failures.
1.i2c_host_mode_toggle.88815822957908182965184092194160678503160647659156919247555082499322288046250
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 80478617 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9310
3.i2c_host_mode_toggle.27299033805954299417294727989613588970200158686045715428786688911003822581506
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 496651738 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @31838
... and 14 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
0.i2c_target_hrst.101482984291276624274144614876058237079118761713409415130092462038902059196277
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10209239870 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10209239870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.108020737111502890758843990728407136347228435825963235410318607425998340661041
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10217638847 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10217638847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
1.i2c_target_stress_all_with_rand_reset.53048497326959690217346836589499213770647433444239466762777127023658806582553
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11590472312 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 216 [0xd8])
UVM_INFO @ 11590472312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.38496174745926823096519373477847556001284787844802676894944126516348944844286
Line 507, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23921525966 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 122 [0x7a])
UVM_INFO @ 23921525966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 25 failures.
2.i2c_target_unexp_stop.12711512802697378218413625839062504018184148496567969669687270244616125547928
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 161846434 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 63 [0x3f])
UVM_INFO @ 161846434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.98016118040851931655174581066366894094784466264224011900811050786296917080672
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 752960502 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 191 [0xbf])
UVM_INFO @ 752960502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
0.i2c_target_nack_txstretch.74415470418315600790279731771181646456484270234720863700415224309481452710220
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 233890831 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 233890831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.49974463842360459375766943737104966984103184327570994422949708745475215004105
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 728959042 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 728959042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
0.i2c_target_unexp_stop.77232700329522286855548780238896427645263663182678837155464778400342416335506
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1367471797 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1367471797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.59195417654251994160509225913027878237837067522167197946709068853916238652320
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 31622512 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31622512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
0.i2c_host_stress_all_with_rand_reset.40416446426190590304727689783285710748841591441630438825731673209326368117118
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1651764023 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1651764023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.61059056941546597222244671922140120895106788542585756306884402157984496485077
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3655161928 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3655161928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
4.i2c_target_stress_all_with_rand_reset.96095829383538617238148718434696303613635891759971886584624178942258976188692
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1432235102 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1432235102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.10623418742099528795508142448301889003118837437801940336665892628568082147261
Line 474, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12241248511 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12241248511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
4.i2c_host_mode_toggle.8196672595583567941720586010706462351874912822528796200672913732226272312876
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 149944689 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.61363006645215790162032773244015376558379798350644563732037987623899707485530
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 128149366 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:
1.i2c_target_unexp_stop.37165932214100016489201578593977497738113671643849833673358354345335122646969
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 419541120 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 419541120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.28196295019079646148470871279079272159945833980052985390420488919860954658139
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 247064558 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 247064558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
6.i2c_target_stress_all_with_rand_reset.55534134527122226829599865599474673798677476938927758387598041570717890859033
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:66f0ce86-88df-461b-9f81-715b2da9573d
7.i2c_target_stress_all_with_rand_reset.34874387272894542935493875744116033061909903928282970740639562096959356200280
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ce246ac2-58ce-4073-b4ed-27230246d1b3
... and 1 more failures.
16.i2c_host_stress_all.65241975858118778874461859145868483521652774247960480032652662902073304942989
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
Job ID: smart:18b85428-5b3d-4f09-807e-2c8eaaa56cee
19.i2c_host_stress_all.12448808065387471661856082295195280272445827164097835534872893261984394815156
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
Job ID: smart:f8c4f703-49ae-488a-aeda-bb75fa2f8345
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
11.i2c_target_stretch.52488923761128521837188864663000313185334094154155871677994774794607437425575
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10040109787 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10040109787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stretch.84104701738158384071037274983240289278326904216066662325967926250882211170766
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10005322416 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10005322416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
11.i2c_host_mode_toggle.53233336189646368260677385686456421527545939489714107526516810891198945352287
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 39816084 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe5bebe94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 39816084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_host_mode_toggle.79257313027295437885278348802085429848608759831589143732285479134412338128934
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 132841935 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x39130e14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 132841935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
8.i2c_host_stress_all.276425926820275922212571362385474653220058767386794714586545640770115490953
Line 463, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 12178748904 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4909199
32.i2c_host_stress_all.87103635823867122911186063075505589554355411510205897360916161333532130616369
Line 390, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 27271687484 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12958033
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
16.i2c_target_stress_all.97866021142343374067694975435058543715284831312060766772144952159452986059506
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 33374628499 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 33374628499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_target_stress_all.36654633374229573556154263995636563322352077813431278843990600882002341751420
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 63835038169 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 63835038169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
0.i2c_target_stress_all_with_rand_reset.106317582268315965652272437856159675792640853972776444218077729427113344741163
Line 398, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 119073046283 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 119073046283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
2.i2c_target_stress_all_with_rand_reset.21371434834254473226578641129287051023433356524983012303659168075433080225035
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1923228700 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1923228700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
9.i2c_target_bad_addr.114475612428771453621887233296964334182435546501496306654850965845045640797767
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
36.i2c_host_mode_toggle.74705199319934550421273219372436960334547977826370642648371054525356575812595
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.