eca25c0ff8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.644m | 8.300ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.740s | 5.497ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 85.296us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.800s | 28.629us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.000s | 2.166ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.820s | 147.561us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.490s | 35.092us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.800s | 28.629us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.820s | 147.561us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 17.520s | 371.344us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 49.767m | 59.470ms | 18 | 50 | 36.00 |
| V2 | host_maxperf | i2c_host_perf | 45.093m | 73.557ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.750s | 24.393us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.244m | 5.026ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.286m | 3.550ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.400s | 180.709us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.630s | 1.864ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.850s | 500.027us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.527m | 7.354ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 40.230s | 892.604us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 10.320s | 243.543us | 14 | 50 | 28.00 |
| V2 | target_glitch | i2c_target_glitch | 13.070s | 2.657ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 38.849m | 61.113ms | 47 | 50 | 94.00 |
| V2 | target_maxperf | i2c_target_perf | 8.650s | 1.163ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.095m | 1.406ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.570s | 1.685ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.950s | 275.237us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.750s | 251.555us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 55.234m | 70.400ms | 49 | 50 | 98.00 |
| i2c_target_stress_rd | 1.095m | 1.406ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.115m | 18.609ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.100s | 5.918ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.776m | 4.901ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.860s | 6.831ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.100s | 10.243ms | 20 | 50 | 40.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.520s | 2.430ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.720s | 304.875us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 45.093m | 73.557ms | 47 | 50 | 94.00 |
| i2c_host_perf_precise | 24.845m | 24.440ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 40.230s | 892.604us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 12.520s | 1.108ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.290s | 1.926ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.930s | 610.390us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.760s | 782.019us | 38 | 50 | 76.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 27.810s | 657.383us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.680s | 2.374ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 18.005us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 21.941us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.490s | 151.433us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.490s | 151.433us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 85.296us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.800s | 28.629us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.820s | 147.561us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 379.122us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 85.296us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.800s | 28.629us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.820s | 147.561us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 379.122us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1664 | 1792 | 92.86 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.400s | 289.175us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.030s | 68.709us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.400s | 289.175us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 6.981m | 92.477ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.070s | 1.086ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 15.536m | 39.140ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1844 | 2042 | 90.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 27 | 55.10 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.40 | 97.37 | 89.91 | 97.22 | 72.62 | 94.47 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:
1.i2c_host_mode_toggle.102680740839695382423464100317259396979316425304998280361635176611907347441729
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 549628637 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @72418
2.i2c_host_mode_toggle.92361948676156712728208858168257137223881665050906476587658472463283615148459
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 629997375 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @11800
... and 16 more failures.
2.i2c_host_stress_all.86999524857234602890211023203618060104318866502708973300655177449646479430607
Line 376, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10527074266 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2749135
3.i2c_host_stress_all.1302138869000831222882969000414786079237438752018200835981682591831299185026
Line 372, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 13049969100 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1995327
... and 18 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
0.i2c_target_hrst.76654041711386536099499439507491172894954425855717295355243391099231899965124
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10040643600 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10040643600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.35930419139310019079207488051792324654878560513258963920831903871951776368219
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11224854351 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11224854351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 25 failures:
0.i2c_target_unexp_stop.98391527045626814590455406552482012708110522296572251329368142854425239752538
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 81860313 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 40 [0x28])
UVM_INFO @ 81860313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.100900668108529419689852291531312348510975277233049632510054612701316844172082
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 321368375 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 49 [0x31])
UVM_INFO @ 321368375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
4.i2c_target_unexp_stop.21977187918064740529229809318200500114104122322819140740998967240300191733089
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 205792525 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 205792525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.104310805463790655042375755999202575680550236014021090116202603605916604984368
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 137765541 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 137765541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.16019971611292958362931621519721470406663374662553200737340337807466485637255
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 348099505 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 348099505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all_with_rand_reset.5830754904040698173780435245113683092918148830742318599502039643042517575355
Line 420, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 92477491919 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 92477491919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.i2c_target_stress_all_with_rand_reset.47847392448104363454465392148480390841399598920009985563326941814683402586959
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 279617297 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 279617297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.4131136613499614542009656422835983138543429689110602628456996244574484502064
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15428698304 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15428698304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 12 failures:
1.i2c_target_nack_txstretch.112925751708125014159806194641939296504252335871623524779145146379839643124611
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 685220757 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 685220757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.42623369863699047738534977190551893660605218891242344310315790835111345826014
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 146054606 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 146054606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
1.i2c_host_stress_all_with_rand_reset.64778638085401281605668840233385251199255435770990915307789226248886286838697
Line 288, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19903923249 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Test i2c_host_mode_toggle has 9 failures.
3.i2c_host_mode_toggle.17514325428383901950276698493245803232940767168075648362556671218707384311359
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 147907577 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
27.i2c_host_mode_toggle.110154706363380590374349164928200707889412200670285619119913375442979131850195
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 175368080 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test i2c_host_stress_all has 3 failures.
1.i2c_host_stress_all.66726016703788620154079826961011116772369133808318471920328536566795266094789
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:6498e40f-ac33-444b-89ee-e3df102168c9
24.i2c_host_stress_all.96164185805912705156310852853054814261190034590631354913692766311667357301264
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
Job ID: smart:5859462c-8e53-4c47-a5ba-570011564846
... and 1 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
1.i2c_target_stress_all_with_rand_reset.93699159124381689113931764480744309660892204324098376093506128915800869256743
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:fb38d7f9-44b0-4c46-9787-d38339e6cbd2
8.i2c_target_stress_all_with_rand_reset.62846385417890868655894238769019175373376692373442925687800125228138386645310
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9fd37c5c-ab33-4dfb-bb89-5099f5c525d8
Test i2c_host_perf has 3 failures.
3.i2c_host_perf.48865394353935119426166944760064637219838310451580884059229571967214721902099
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_perf/latest/run.log
Job ID: smart:5a709bb6-ea50-4364-877a-2c16aaf0ed88
39.i2c_host_perf.58880949849032029644528797902035219991025938915681835210388363223850598889231
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_perf/latest/run.log
Job ID: smart:6c6b39ab-835a-4fc9-a3b6-f53b36cb9c06
... and 1 more failures.
Test i2c_target_stress_wr has 1 failures.
15.i2c_target_stress_wr.94267761359423122173637336988571737049676643370871561942690065069767305803113
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_wr/latest/run.log
Job ID: smart:50e2cf63-bb98-4a71-b8bd-6aaa3f912a32
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:
2.i2c_target_unexp_stop.104075341108027283434636782452675687186797431768126711840736728391755724983213
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 430966604 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 430966604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.88267334302881257349819071009026767614579813189067185079290813441983707230095
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 414402809 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 414402809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
0.i2c_target_stretch.12840821541832513404133459050308414953268430297332172217718472565936236545429
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011817068 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011817068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stretch.28439748269318740442029869824660109657910144665756447858375298119285886227239
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002945277 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002945277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 6 failures:
0.i2c_host_mode_toggle.2196913360793586815432873459010341848569286131962289647346612732211336026543
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 138070873 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xabc33294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 138070873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_host_mode_toggle.113329306007450645741387925204945129207068551743940183258110247032049687726676
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 86197509 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc604514, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 86197509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
15.i2c_host_stress_all.107045334035085229933014125012762204911752761230524953592987233239551412059669
Line 388, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 118194774960 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @36104845
17.i2c_host_stress_all.32572099449989047044033548326103544098097906712025202768199236208336240516197
Line 417, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 22056731612 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3231583
... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 4 failures:
5.i2c_target_stress_all.91665781881057492463566370577292939374740201651137950255134318451458703476015
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 51293810689 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 51293810689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stress_all.949025301496320299292298179738001697996970058158189271413120719623099277242
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 61113131398 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 61113131398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
29.i2c_target_intr_stress_wr.60784378936022989397585336725772594662538129794476810425009745878298197626779
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 20883095945 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 20883095945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
Test i2c_target_fifo_watermarks_tx has 2 failures.
6.i2c_target_fifo_watermarks_tx.8079537876090093171703891640419811981214521265715489910459258151309823409556
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
45.i2c_target_fifo_watermarks_tx.56952720569336881652832768336978172194327478490100920879252109785909891482116
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 2 failures.
12.i2c_target_tx_stretch_ctrl.57198727167011865120627839742723477049785963661243675982187066391223874256835
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
45.i2c_target_tx_stretch_ctrl.66736692530801743838872138683957040597078764690290663999466923186501133119915
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Exit reason: Error: User command failed Error-[NOA] Null object access has 3 failures:
10.i2c_host_mode_toggle.53961845880669993820466402718406665826011454659019106352736855409520359411661
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
38.i2c_host_mode_toggle.53502805647899387526897909037248352517614830470292978250478129157655035713776
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
... and 1 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
2.i2c_host_stress_all_with_rand_reset.92307215546541995229062482265665412615794217942978664846479193925822454976015
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 280629775 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (5 [0x5] vs 3 [0x3])
UVM_INFO @ 280629775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred! has 1 failures:
2.i2c_target_stress_all_with_rand_reset.50373978709075806429023206409211216445294542316395780422385220357890225867302
Line 440, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 80565814053 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 80565814053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
9.i2c_host_stress_all.73100200723842528300405400537222247066388462799301719297784443936696297375949
Line 315, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18803750017 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
9.i2c_target_stress_all_with_rand_reset.72643210767751789148599137990198152173295587573561675184886820896508875922719
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4483108849 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4483108849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
14.i2c_host_stress_all.106427509339350214757437754153703778362999086723613606446784197757949530645289
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
25.i2c_host_stress_all.20717858085284192359580079166944188648747662008428249614382960626337816646247
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 63400793 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (0 [0x0] vs 2 [0x2])
UVM_INFO @ 63400793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---