I2C Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.731m	2.129ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	46.870s	1.878ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	24.237us	5	5	100.00
V1	csr_rw	i2c_csr_rw	5.347m	177.751ms	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.870s	1.289ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.990s	106.286us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.730s	46.314us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	5.347m	177.751ms	20	20	100.00
		i2c_csr_aliasing	1.990s	106.286us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	12.350s	2.865ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	52.660m	86.933ms	24	50	48.00
V2	host_maxperf	i2c_host_perf	25.253m	24.998ms	50	50	100.00
V2	host_override	i2c_host_override	0.770s	28.672us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.075m	19.689ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.989m	9.402ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.380s	163.923us	50	50	100.00
		i2c_host_fifo_fmt_empty	27.760s	2.127ms	50	50	100.00
		i2c_host_fifo_reset_rx	13.870s	242.225us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.771m	7.198ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	44.140s	2.009ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.040s	272.467us	21	50	42.00
V2	target_glitch	i2c_target_glitch	11.090s	4.070ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	59.335m	63.805ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	6.640s	8.549ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.312m	1.720ms	50	50	100.00
		i2c_target_intr_smoke	9.290s	3.279ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.000s	274.313us	50	50	100.00
		i2c_target_fifo_reset_tx	1.760s	3.418ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	56.003m	65.804ms	50	50	100.00
		i2c_target_stress_rd	1.312m	1.720ms	50	50	100.00
		i2c_target_intr_stress_wr	12.923m	23.239ms	48	50	96.00
V2	target_timeout	i2c_target_timeout	8.040s	5.490ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	5.061m	5.147ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	7.350s	1.384ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	36.730s	10.175ms	29	50	58.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.380s	628.829us	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.620s	469.410us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	25.253m	24.998ms	50	50	100.00
		i2c_host_perf_precise	14.707m	23.178ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	44.140s	2.009ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	14.600s	1.265ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.260s	2.473ms	50	50	100.00
		i2c_target_nack_acqfull_addr	2.930s	2.158ms	50	50	100.00
		i2c_target_nack_txstretch	1.810s	454.819us	32	50	64.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	38.460s	924.073us	50	50	100.00
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.620s	566.835us	50	50	100.00
V2	alert_test	i2c_alert_test	0.690s	52.654us	50	50	100.00
V2	intr_test	i2c_intr_test	0.770s	18.246us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.250s	191.418us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.250s	191.418us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	24.237us	5	5	100.00
		i2c_csr_rw	5.347m	177.751ms	20	20	100.00
		i2c_csr_aliasing	1.990s	106.286us	5	5	100.00
		i2c_same_csr_outstanding	1.200s	585.566us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	24.237us	5	5	100.00
		i2c_csr_rw	5.347m	177.751ms	20	20	100.00
		i2c_csr_aliasing	1.990s	106.286us	5	5	100.00
		i2c_same_csr_outstanding	1.200s	585.566us	20	20	100.00
V2		TOTAL			1686	1792	94.08
V2S	tl_intg_err	i2c_tl_intg_err	2.240s	269.998us	20	20	100.00
		i2c_sec_cm	0.940s	75.728us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.240s	269.998us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.796m	8.255ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.470s	6.620ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.687m	55.426ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	70	0.00
		TOTAL			1866	2042	91.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	49	38	28	57.14
V2S	2	2	2	100.00
V3	4	3	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.40	97.37	89.80	97.22	72.62	94.47	98.44	89.89

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 37 failures:
- Test i2c_target_unexp_stop has 36 failures.
  - 0.i2c_target_unexp_stop.101727737144779130659599327509370746056779857291249746230528697678114523299589
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 102994931 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 127 [0x7f])
  UVM_INFO @ 102994931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_unexp_stop.96657034312593377509312032980351711161376813849031803899263435723528832235303
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 225834541 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 92 [0x5c])
  UVM_INFO @ 225834541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.29075183472725218000552411302586717213469301905757281219616461446847881074307
    Line 537, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55426345244 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 162 [0xa2])
  UVM_INFO @ 55426345244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 34 failures:

Test i2c_host_mode_toggle has 16 failures.

0.i2c_host_mode_toggle.86599051508536882636710539018015363522758452294642358014222138243342361060793
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 112615597 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7378

1.i2c_host_mode_toggle.67645146008874139260796604197255476114380304878159404027756164555564976826680
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 158837632 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @29504

... and 14 more failures.

Test i2c_host_stress_all has 18 failures.

1.i2c_host_stress_all.23629618387163384158339173668102418718391213930637703871042187148286308194100
Line 430, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 12836944891 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13142761

3.i2c_host_stress_all.114416562181243103038374318740641303354388158128716585065191546884491829298716
Line 424, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 31202164137 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10844241

... and 16 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 21 failures:
- Test i2c_target_hrst has 21 failures.
  - 0.i2c_target_hrst.77650425447880311009111421082847847197970781369309528199600895942259729561080
    Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10263379118 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10263379118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_hrst.102184800244704154173414980844714001883158179971455679098995556413934005487772
    Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10530417287 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10530417287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
- Test i2c_target_nack_txstretch has 18 failures.
  - 1.i2c_target_nack_txstretch.50632846252177600019565263924959041146245656707437484207171199452011473442121
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 213360304 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 213360304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_nack_txstretch.80369739605662480965142767462019240041335869299637013352758947113673462173719
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 150478293 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 150478293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:839) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:

Test i2c_host_stress_all_with_rand_reset has 7 failures.

0.i2c_host_stress_all_with_rand_reset.12796496875040520179669259841896150093031009914146926391843591535680130390312
Line 375, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36194934150 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36194934150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.81184419091336469971803386987294914900146988520811062648979571565560101148961
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3059154768 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3059154768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

1.i2c_target_stress_all_with_rand_reset.33004921499694518339718048938540058296428507893635209727443421535406224339893
Line 388, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37255176318 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 37255176318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.104337175395034512956855619130974825211560785880700786342369090964490848278299
Line 717, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29226370031 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29226370031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test i2c_host_stress_all has 7 failures.
  - 0.i2c_host_stress_all.108246832195285116591716592856286707664619589303667296924003259240516447481135
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:03c2ded3-cab1-470a-9660-38ecedca98c8
```
  - 12.i2c_host_stress_all.43052400276646687737820531566561263702012920647946186335294955076571086892902
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:2143d7f0-e163-4c64-8f61-ae2d2a887bb0
```
  - ... and 5 more failures.
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_host_stress_all_with_rand_reset.95503827846005298802367439142074565439892062041167801576927810999852218687806
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3edc15f0-fec2-4656-a585-9597d3e48ff8
```
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 3.i2c_target_stress_all_with_rand_reset.69985429605041664135717815371409721649944401366916859315278894757210585449533
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:13a19c5c-4f8e-4925-91be-c7e9750fefe2
```
  - 8.i2c_target_stress_all_with_rand_reset.37993780525426052247863030729820439954538847079888170326449995782924163910936
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0f8e5a17-5429-4f6e-bf53-be116bf4be44
```
- Test i2c_target_stress_all has 1 failures.
  - 42.i2c_target_stress_all.52813561776357002804353651109734435118981613818530320152619398160669689838031
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:0478744e-68e5-4bb6-ba17-ab51cdfbb2ca
```

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:

Test i2c_host_mode_toggle has 8 failures.

7.i2c_host_mode_toggle.16485187937683616545111824000894097854142103285827196387827023286372098118140
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  62349472 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

12.i2c_host_mode_toggle.36195359381994413308933308099962004354387358096874370193434618909780716043286
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 237135038 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 6 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:

Test i2c_target_unexp_stop has 7 failures.

1.i2c_target_unexp_stop.104989774444700374202183917919882925520713306887251151043771448274792730134287
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 178905544 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 178905544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_target_unexp_stop.107117708013537111195581664874538751794687226629573761093478446348449926224953
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 221637094 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 221637094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 7 failures:
- Test i2c_target_unexp_stop has 7 failures.
  - 6.i2c_target_unexp_stop.70745270723624251787811288933767565878331061217042940694219162987006706716499
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 485406212 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 485406212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.i2c_target_unexp_stop.41647049139315037660263507407812582208702571897828161228221425572528891215676
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1677226892 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1677226892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 3.i2c_host_mode_toggle.22083655544939550210311515233154211043659671005804551506629241664721893683784
    Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 158993594 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xcc190a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 158993594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_host_mode_toggle.57200151583093112643937821912629847949828578563079879398560783783637575754975
    Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  27102679 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4c0ac814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  27102679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 6.i2c_target_tx_stretch_ctrl.377411607019145646961205125327764717818440154681035453398520354544756748664
    Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 46.i2c_target_tx_stretch_ctrl.8835552801195757121747207564259581929715550074418298937356780926421623588848
    Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 44.i2c_target_fifo_watermarks_tx.115255060046790542699178875870836583885893709370980139582307620197076854642206
    Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 7.i2c_target_stretch.29568535572356144365091199133534624586818949516945451679915833000269876860031
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011512493 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011512493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.i2c_target_stretch.1970201672082993640374974826797938378282087767883295219995158344622595364994
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011105284 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011105284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 2 failures.
  - 8.i2c_host_stress_all_with_rand_reset.89564729561797308694000160444315964264009535601015430068424833311649758126457
    Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3580097596 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
  UVM_INFO @ 3580097596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.i2c_host_stress_all_with_rand_reset.21244946629151674435590859298185572986203957210051353406869470353000684327344
    Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7758984728 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (6 [0x6] vs 3 [0x3])
  UVM_INFO @ 7758984728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_intr_stress_wr has 2 failures.
  - 35.i2c_target_intr_stress_wr.18646184656750110646530578339953532396113593670461646143384256988589296117719
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 26669478255 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 26669478255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.i2c_target_intr_stress_wr.758516897125723022723970585623094176259056461306824084858090626448203975215
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 12402966859 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 12402966859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_env_pkg.sv:93) [i2c_env_pkg::acq2item] Check failed data >> * == '* (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 5.i2c_target_stress_all_with_rand_reset.61780246442956534491636936412102248491657569942548694674304408865933173879059
    Line 314, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9171699382 ps: (i2c_env_pkg.sv:93) [i2c_env_pkg::acq2item] Check failed data >> 11 == '0 (2097151 [0x1fffff] vs 0 [0x0])
  UVM_INFO @ 9171699382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_target_stress_all_with_rand_reset.48149708418960669426196787500896702316659729094153783000610460448322705056943
    Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2616616563 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2616616563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 18.i2c_host_stress_all.96244151698314280760375128530611145896760586237133760867048429366837714975454
    Line 403, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 31602788572 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @15679015
```
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 24.i2c_host_mode_toggle.21072340372124728619128582965367660753315159481195196066875861647909616055903
    Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 31.i2c_target_bad_addr.18004586417436217424980588811083831051546102663942984107586634878121600526279
    Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```