39f3866b56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.764m | 10.246ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 46.790s | 3.322ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.770s | 49.234us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.860s | 21.246us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.970s | 2.019ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.830s | 156.598us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.580s | 103.432us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.860s | 21.246us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.830s | 156.598us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 19.850s | 506.198us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.822m | 113.229ms | 12 | 50 | 24.00 |
| V2 | host_maxperf | i2c_host_perf | 50.283m | 29.448ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.730s | 29.398us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.629m | 5.389ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.064m | 10.512ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.450s | 183.965us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 29.140s | 1.222ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.490s | 1.202ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.882m | 12.700ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 42.290s | 1.762ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.170s | 648.644us | 19 | 50 | 38.00 |
| V2 | target_glitch | i2c_target_glitch | 10.060s | 5.600ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 53.545m | 63.825ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 8.550s | 4.562ms | 49 | 50 | 98.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.345m | 6.317ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.990s | 3.019ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.080s | 300.624us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.910s | 980.467us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 43.020m | 61.029ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.345m | 6.317ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 13.526m | 28.165ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.380s | 5.505ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.199m | 4.266ms | 49 | 50 | 98.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.370s | 1.221ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 35.550s | 10.116ms | 23 | 50 | 46.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.460s | 2.497ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.750s | 396.725us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 50.283m | 29.448ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 51.323m | 23.202ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 42.290s | 1.762ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 21.840s | 1.797ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.280s | 1.225ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.060s | 564.552us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.660s | 248.549us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 24.890s | 1.201ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.670s | 573.246us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.750s | 29.021us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 21.657us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.720s | 173.409us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.720s | 173.409us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.770s | 49.234us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 21.246us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.830s | 156.598us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 59.120us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.770s | 49.234us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 21.246us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.830s | 156.598us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 59.120us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1678 | 1792 | 93.64 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.340s | 244.218us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.950s | 193.199us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.340s | 244.218us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 14.236m | 55.955ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.780s | 2.595ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 14.462m | 107.237ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1858 | 2042 | 90.99 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.43 | 97.30 | 89.73 | 97.22 | 72.62 | 94.40 | 98.44 | 90.32 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 48 failures:
0.i2c_host_stress_all.95847156483890124075025801220867528419367758565060267670811217414135290221842
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 29716210328 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4002935
1.i2c_host_stress_all.70899383966784370181679244950663497035892050064738624557051272789728397146465
Line 366, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10474880070 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10642685
... and 26 more failures.
3.i2c_host_mode_toggle.87494601535312719469850222884822020038569915619042091806011908424063979060811
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 648643552 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @94938
4.i2c_host_mode_toggle.14122012683067538740836601858423984284212467857618119819324572891788966025664
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 69388046 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @19540
... and 18 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
4.i2c_target_unexp_stop.98817004522216160166762165193182780361247428942898803902670939343167179099490
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 627937297 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 198 [0xc6])
UVM_INFO @ 627937297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.22826959896523236070812080155001803041601753969363655215172253650166944175808
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 207188797 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 157 [0x9d])
UVM_INFO @ 207188797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
4.i2c_target_stress_all_with_rand_reset.69709449395363700058604211309867117720027719879564471387637084469149046070686
Line 461, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35000054114 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 58 [0x3a])
UVM_INFO @ 35000054114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.109092351096039731471040826690833475983077289351449224402215219470684105411126
Line 763, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30733029477 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 127 [0x7f])
UVM_INFO @ 30733029477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
4.i2c_target_hrst.22687893861371012693257359848938307345069406795730009680135549422725273606361
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10213315517 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10213315517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_hrst.42659814282795045503555076187823751865624734440583976710292516006871964382060
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10413145972 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10413145972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
0.i2c_target_unexp_stop.14673476257917536964231417659779385719918299361163342766911796807958337480671
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 359930246 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 359930246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.13554833852360499530686469297316365136244601963743103702605331970745554282287
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 195535081 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 195535081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
4.i2c_target_nack_txstretch.99373128000763137735714083948314562723351566342782552181627630207470422711792
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1018086269 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1018086269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_nack_txstretch.75985420899627926444028031061599813943612349045840980813650670483608749384818
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 282980108 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 282980108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
0.i2c_host_stress_all_with_rand_reset.15123816904556817376032222597766932689350492382555584279701528366672261336382
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1492084245 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1492084245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.49093062675529505324796643315345510610978756283463296907556270447971832962267
Line 351, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24417577988 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24417577988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_stress_all_with_rand_reset.13888835590668274593100827445960762098598359028538801020286858345148855141853
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4362610414 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4362610414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.47791354130942859628177415321049094361108901161127304088131035804196300092970
Line 352, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6768734251 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6768734251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:
0.i2c_host_mode_toggle.18901755861729629946493401263573456754148977788215765618063142176428286339951
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 33437175 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
1.i2c_host_mode_toggle.63918886205033264590358989596704075542666427776175458376126571663840109872287
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 304662635 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:
5.i2c_target_unexp_stop.56085575501745446395859160679809652197277504905722995573749750591000254991957
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 400161665 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 400161665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_unexp_stop.38879044161711279824385164813615220454227158103995221133698319229766577745295
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 134072777 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 134072777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
9.i2c_host_stress_all.85007091618510641517434007147054976968865452327773808120175573242195921122998
Line 444, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 51960916913 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5920175
30.i2c_host_stress_all.103516494359188942992255746073981742666822527803465816278874674793558052197829
Line 446, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 33673583423 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17226265
... and 4 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
0.i2c_target_stress_all_with_rand_reset.108675126684921830773224957926770504304333072332577526943753286648943849278092
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ee6bf236-2916-47fb-98ca-653863288952
6.i2c_target_stress_all_with_rand_reset.48851764798785234021500741935024540502946578660150753726317280161093891470689
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:eb7f547f-7339-43ec-849b-d6691f68bff7
Test i2c_host_stress_all_with_rand_reset has 1 failures.
1.i2c_host_stress_all_with_rand_reset.75638132359186031624214648052945464640263041077406098887336636409601483668850
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:113d41b6-1378-4b73-8713-43253ab41cfd
Test i2c_host_stress_all has 2 failures.
11.i2c_host_stress_all.34965210857107864631827763090919412076947344186897195761239433565600010214242
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
Job ID: smart:e5bf8058-d0cc-49ff-9bbc-4db6694e4dd9
43.i2c_host_stress_all.1622946545897370806847752547130934925491334461349546426050011067532955192254
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
Job ID: smart:bff0e4f9-7372-48d9-9d1e-140e03827e77
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test i2c_target_perf has 1 failures.
13.i2c_target_perf.111840234203446377495496087103944175485780328110594462784980735786579424954608
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 2 failures.
21.i2c_host_stress_all.21378126746634329965076156591226425601919661563752971645467707211146241929524
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_host_stress_all.19291134234091115504015391584628014854577515724146097855299118795408897940412
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
10.i2c_target_fifo_watermarks_tx.105499426058357917621480520413128984148706083632608201509387266303306567687853
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
27.i2c_target_tx_stretch_ctrl.47865733123745890472949696571787989664624136420004713272876264250890733386618
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
32.i2c_host_mode_toggle.66713829933283959349655124346345014907846990440008612635198091132854976637464
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 123755262 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x2270fb14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 123755262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_host_mode_toggle.56731559931193470788295861621871698558272597365899235686083935471691990909031
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 220274196 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x98c13e94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 220274196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
2.i2c_target_stress_all_with_rand_reset.46782395117668351716448859763899982257474270617368828338394094570369077937151
Line 747, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 552320976143 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 552320976143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_env_pkg.sv:93) [i2c_env_pkg::acq2item] Check failed data >> * == '* (* [*] vs * [*]) has 1 failures:
8.i2c_target_stress_all_with_rand_reset.109965824160537237813572191506650346099274808856540740205830707609225510767773
Line 471, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36885003800 ps: (i2c_env_pkg.sv:93) [i2c_env_pkg::acq2item] Check failed data >> 11 == '0 (2097151 [0x1fffff] vs 0 [0x0])
UVM_INFO @ 36885003800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
22.i2c_target_stretch.13178581767823536041615664906050609643655443121708970636368120404316837979495
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10003414777 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10003414777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---