fdfa12db04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.836m | 10.166ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 51.690s | 5.303ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.820s | 70.273us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.850s | 44.894us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.720s | 760.808us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.940s | 265.792us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.390s | 29.288us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.850s | 44.894us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.940s | 265.792us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 9.190s | 1.326ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 47.584m | 125.504ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 48.706m | 51.518ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.770s | 80.344us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.272m | 5.112ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.534m | 5.234ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.410s | 350.225us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 22.980s | 1.729ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.440s | 514.706us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.901m | 7.307ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 40.920s | 1.715ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.450s | 381.048us | 19 | 50 | 38.00 |
| V2 | target_glitch | i2c_target_glitch | 10.650s | 8.135ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 56.212m | 72.570ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 8.390s | 4.898ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.129m | 1.465ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.940s | 2.907ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.820s | 289.586us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.010s | 514.615us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 41.842m | 61.724ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.129m | 1.465ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.022m | 21.856ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.450s | 3.202ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.956m | 4.509ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.180s | 7.903ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 35.870s | 10.004ms | 29 | 50 | 58.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.650s | 635.851us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.670s | 205.106us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 48.706m | 51.518ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 15.313m | 23.247ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 40.920s | 1.715ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 11.430s | 1.015ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.330s | 561.947us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.990s | 1.954ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.810s | 233.920us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.150s | 740.041us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.630s | 1.098ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.710s | 29.654us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.710s | 51.599us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.730s | 127.580us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.730s | 127.580us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.820s | 70.273us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 44.894us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.940s | 265.792us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 62.495us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.820s | 70.273us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 44.894us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.940s | 265.792us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 62.495us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1679 | 1792 | 93.69 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.400s | 451.929us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.050s | 114.210us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.400s | 451.929us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 18.268m | 110.710ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.620s | 4.178ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.262m | 205.089ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1859 | 2042 | 91.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.38 | 97.27 | 89.69 | 97.22 | 72.62 | 94.33 | 98.44 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 40 failures:
0.i2c_host_stress_all.12339985294383190959638650866975514129762919902953873115502798553128097465403
Line 342, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 54094334857 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @34234369
1.i2c_host_stress_all.108198308178562196295216184685679382036604850220400881839929711179088356156118
Line 298, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 22030534558 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3084469
... and 22 more failures.
0.i2c_host_mode_toggle.4503394145830310355424045996675426758914531648030243443517463441987579135267
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 128415010 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21072
16.i2c_host_mode_toggle.4416899848541854513316361759395848872980172090892757111220311907792234499266
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 89979934 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @47702
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
0.i2c_target_unexp_stop.85042099619181176189819614489222248218834143769986861722246592517807825303486
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 165757491 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 224 [0xe0])
UVM_INFO @ 165757491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.1198857516400172222279528486920283951530883204990244023468819236095648765565
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 44095562 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 187 [0xbb])
UVM_INFO @ 44095562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
1.i2c_target_stress_all_with_rand_reset.23179092826051368416272480470995250392822712266636803775369218906516029141734
Line 343, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34831763509 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 66 [0x42])
UVM_INFO @ 34831763509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 21 failures:
2.i2c_target_hrst.61306347393832174424578726988782243878815330998737635941554818415865058080399
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10099693949 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10099693949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_hrst.63639345599216062929072967843909458759005730490988272997388979989852862881994
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10862476961 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10862476961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
4.i2c_target_unexp_stop.84482057272573826563590085040709037864770811076539729745054538305089500842150
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 209842907 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 209842907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.71479632021627381724917584115587332145831801297647098209918913501363373715599
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 17519893 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 17519893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
0.i2c_host_stress_all_with_rand_reset.3626531299176513453807412437579405976986745246033324396468024293256875091618
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4251341298 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4251341298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.98904849788363388883401103999975090893200696311428615525582791599409407804840
Line 347, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8180082015 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8180082015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.39709607206362500599482921908260888418668090559782735932994827916197004934261
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7252806497 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7252806497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.76369395788722744858735977680378882793903305699498298052812737056506864284922
Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11089573189 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11089573189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
2.i2c_target_nack_txstretch.95839778975068242723431840333094427699816175258794389235421383843482872862864
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 233919607 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 233919607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.19824501732681386224511552857816453118570026262884012535771644156141242091160
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 173630032 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 173630032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:
4.i2c_host_mode_toggle.32518814419205674182540118974544715695986616393435551632807701455663683054302
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 741320005 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.14820127030329773767965814432989158015513908442406153757690381400278854743740
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 282917531 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
2.i2c_target_stress_all_with_rand_reset.30059228319691360999968647528649027695823799769344081128299833935390198015192
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:25fffe38-aeee-45b8-a59a-92a20410cfae
Test i2c_host_stress_all has 6 failures.
4.i2c_host_stress_all.25989753931475409536851766576395917231358282032592768232863126690608925840795
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
Job ID: smart:1d090ae2-57b9-4db8-a197-79ecee800ea9
15.i2c_host_stress_all.67704415037474374389845317056820042937180783054057409213174341622193716029741
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
Job ID: smart:749b4767-0d3a-48a1-85f6-e1eb93787f90
... and 4 more failures.
Test i2c_host_perf has 2 failures.
16.i2c_host_perf.19509342749741822361684764512947597621022413654211420052582652146541328032964
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_perf/latest/run.log
Job ID: smart:d59e4fc4-8f50-4ff8-b647-d6c7a68acf73
17.i2c_host_perf.54550784973616362272000633975576775608407175044700480834626449695965165307365
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_perf/latest/run.log
Job ID: smart:c3086eae-c58f-472a-a2e9-e7a7fbe9bb3a
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
12.i2c_target_tx_stretch_ctrl.2391944479522777409895831111155141933125372651878432672652415338830787381748
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
16.i2c_target_tx_stretch_ctrl.79880301431293208840479086767557058094605192113159806253719226602251651075739
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
31.i2c_target_fifo_watermarks_tx.38605370770293103680312689431514354169590534472091429017026635225021279799754
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
14.i2c_target_unexp_stop.72305986735525789864118601031017257149480789967826188393812645606043307977873
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 139346288 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 139346288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_unexp_stop.115630103396073991936848496761216611116825432342139898821578446400420322495550
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 233508101 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 233508101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
2.i2c_target_stretch.56284504328510219249556654182955402092207376314597125372543704524502681125488
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001889855 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001889855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stretch.46303559491650893705927440656547247960866662597729936783296132197785155689227
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012917027 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012917027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
11.i2c_host_stress_all.35585032793219767021256909722225511911433441729204884742678692527977456811419
Line 397, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 53947645361 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12166937
20.i2c_host_stress_all.38161567713819478693063624725463669835305120338704373425043235602019170620671
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 23785236113 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7265857
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
3.i2c_target_stress_all_with_rand_reset.21349263380098104509183428705780554336694082528902732310883519430902650328587
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 897189388 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 897189388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.107204898149811746918279347293377381684179967110188569244270171088067816047759
Line 782, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 205089360054 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 205089360054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
2.i2c_host_mode_toggle.110992680294960012592559954241707972846730233432893315456506055662710479422219
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 95945299 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x19e21f94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 95945299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred! has 1 failures:
5.i2c_target_stress_all_with_rand_reset.16345490244366992957599678367499159527650700480355286774995499995886611399904
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 28046228012 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 28046228012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
16.i2c_target_stress_all.57023896863739963620221739520488432073266533243893747714070369307535153632423
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 57736618979 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 57736618979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
22.i2c_host_stress_all.19920867434664045742541854318797681371708744582838060325646535277909700149792
Line 373, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
25.i2c_host_mode_toggle.77433068128064027592035088383070933896406054048426258851450225784515250488547
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
48.i2c_host_error_intr.94076214878641748127509074635174078756899512651262004334335493167287715990598
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 55545839 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------